Two voltage-mode topologies single input multi-output universal fractional filters with high input impedance are proposed. The proposed analog filters consist of three DVCC+ blocks, two grounded capacitors and two resistors targeting the minimum passive elements. The proposed topologies provide a realization for all standard fractional filter functions (HP, LP, BP, AP and notch filter). The effect of Fractional order on filter responses in the range of \(\alpha\) from 0.7 to 1.2 was studied. Fractional order has been investigated for different filter responses in terms of cutoff, gain, phase and noise. The central frequency was designed to be 110 KHz for the first topology, while that of the second topology is around 100 KHz. The proposed filters are simulated using Cadence TSMC 130nm with dual supply voltages \(\pm \,0.75V\). A performance comparison between the proposed topologies and the topologies in the literature shows that the proposed architecture gives an acceptable performance.

提出了两种具有高输入阻抗的电压模式拓扑单输入多输出通用分数阶滤波器。拟议中的模拟滤波器包括三个DVCC +模块，两个接地电容器和两个针对最小无源元件的电阻器。提出的拓扑为所有标准分数滤波器功能（HP，LP，BP，AP和陷波滤波器）提供了一种实现。分数阶对\（\ alpha \）范围内的滤波器响应的影响从0.7到1.2进行了研究。对于截止频率，增益，相位和噪声，已经针对不同的滤波器响应研究了分数阶。第一个拓扑的中心频率设计为110 KHz，而第二个拓扑的中心频率设计为100 KHz左右。所提出的滤波器是使用Cadence TSMC 130nm和双电源电压\（\ pm \，0.75V \）进行仿真的。所提议的拓扑与文献中的拓扑之间的性能比较表明，所提议的体系结构具有可接受的性能。