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The Configurable Hybrid Precoding Processor for Bit-Stream-Based mmWave MIMO Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems ( IF 2.8 ) Pub Date : 2020-12-01 , DOI: 10.1109/tvlsi.2020.3029626
Hao-Yu Cheng , Chen-Wei Chen , Chung-An Shen , Yuan-Hao Huang

Beamforming technology plays an essential role in the promising millimeter wave (mmWave) massive multiple-input and multiple-output (MIMO) communications for fifth generation (5G) new radio system. Specifically, hybrid analog beamforming and digital precoding scheme can be employed to reduce the excessive radio frequency (RF) chains and data converters in the massive MIMO transceiver while still maintaining optimal spectral efficiency. However, traditional hybrid precoding architecture cannot be configured to support different system specifications, such as the number of bit streams or transmit antennas, leading to the limitation to hardware flexibility and efficiency. This article presents a configurable and low-complexity hybrid precoder based on the parallel data-stream processing in respect of system, algorithm, and architecture. The proposed algorithm was designed to avoid signal dependence between data streams so as to realize configurable precoding architecture. The performance and complexity of the proposed algorithm were also simulated and analyzed in detail in this article. Moreover, the hybrid precoding processor chip was designed and implemented based on the proposed algorithm. A novel data-processing flow was designed in the precoder so as to increase the hardware efficiency and configurability. The designed hybrid precoding chip can be configured to support one to four data streams for $16\times 16$ mmWave MIMO systems. The designed precoder was implemented by using TSMC 40-nm CMOS technology. The normalized throughput achieved 11.1 M channel-matrices per second at a maximum clock frequency of 300 MHz. The area complexity is 263.5 kGE, and power consumption is 119.1 mW.

中文翻译:

用于基于比特流的毫米波 MIMO 系统的可配置混合预编码处理器

波束赋形技术在面向第五代 (5G) 新无线电系统的有前途的毫米波 (mmWave) 大规模多输入多输出 (MIMO) 通信中发挥着至关重要的作用。具体来说,可以采用混合模拟波束成形和数字预编码方案来减少大规模 MIMO 收发器中过多的射频 (RF) 链和数据转换器,同时仍保持最佳频谱效率。然而,传统的混合预编码架构无法配置以支持不同的系统规范,例如比特流的数量或发射天线的数量,导致硬件灵活性和效率受到限制。本文从系统、算法和体系结构方面提出了一种基于并行数据流处理的可配置且低复杂度的混合预编码器。该算法旨在避免数据流之间的信号依赖性,从而实现可配置的预编码架构。本文还对所提出算法的性能和复杂度进行了详细的仿真和分析。此外,基于所提出的算法设计并实现了混合预编码处理器芯片。在预编码器中设计了一种新颖的数据处理流程,以提高硬件效率和可配置性。设计的混合预编码芯片可以配置为支持 16 美元/16 美元毫米波 MIMO 系统的一到四个数据流。设计的预编码器是通过使用 TSMC 40-nm CMOS 技术实现的。标准化吞吐量在 300 MHz 的最大时钟频率下实现了每秒 11.1 M 通道矩阵。面积复杂度为 263.5 kGE,
更新日期:2020-12-01
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