There has been significant recent progress in the implementation of integrated non-reciprocal components based on linear periodically time-varying (LPTV) circuits. Nevertheless, integrated circulators still require a leap forward in power handling, clock power consumption, and insertion loss (IL) to become compelling compared with ferrite circulators or integrated reciprocal alternatives, such as the electrical-balance duplexer (EBD). This article introduces three innovations: 1) a new switched-capacitor clock-boosting scheme; 2) high-Bragg-frequency quasi-distributed transmission lines based on periodically loaded inductors; and 3) a new gyrator based on switched partially reflecting t-lines—which enable significant performance improvement for integrated circulators and for LPTV circuits more broadly. These are showcased in a 1-GHz 180-nm SOI CMOS circulator that exhibits 2.1-/2.6-dB TX-ANT/ANT-RX IL (0.3 dB better than prior art), +34-dBm TX-ANT P1 dB (2.5 $\times $ or 4 dB better), and 40% lower chip area, all at 39-mW power consumption (4.4 $\times $ lower).

中文翻译：

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基于开关电容器时钟提升的多瓦 1GHz CMOS 环行器

最近在基于线性周期时变 (LPTV) 电路的集成非互易组件的实现方面取得了重大进展。尽管如此，与铁氧体环行器或集成互易替代品（例如电平衡双工器 (EBD)）相比，集成环行器仍需要在功率处理、时钟功耗和插入损耗 (IL) 方面实现飞跃。本文介绍了三项创新：1）一种新的开关电容时钟提升方案；2）基于周期性负载电感的高布拉格频率准分布式传输线；3) 一种基于开关部分反射 t 线的新型回转器——它可以显着提高集成环行器和更广泛的 LPTV 电路的性能。 $\times $ 或 4 dB 更好），芯片面积减少 40%，所有这些都在 39-mW 功耗下（4.4 $\times $ 降低）。