The design of cryptographic engines for the Internet of Things (IoT) edge devices and other ultralightweight devices is a crucial challenge. The emergence of such resource-constrained devices raises significant challenges to current cryptographic algorithms. PHOTON is an ultra-lightweight cryptographic hash function targeting low-resource devices. The currently implemented hardware architectures of PHOTON hash function utilize a large amount of resources and have low operating frequencies with a low rate of throughputs. Maximum operating frequency and throughput of PHOTON architecture can be improved but at the cost of larger area utilization. Therefore, to improve the area-performance trade-offs of PHOTON hash function, an iterative architecture is implemented in this work. The concern is with the most lightweight version of PHOTON hash function with the hash size of 80 bits. It is implemented and verified on several Xilinx and Altera Field Programmable Gate Array (FPGA) devices using their synthesis and simulation tools. Low-cost and high-processing FPGA devices were both considered. The design is optimized for performance, whereas the area utilization is also taken into consideration. The overall performance and logic utilization are benchmarked with the existing implementations. The results show an improvement rate of 10.26% to 51.04% in the speed performance and a reduction rate of 7.55% to 60.64% in area utilization compared to existing implementations of PHOTON hash functions.

中文翻译：

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适用于物联网边缘设备的基于 FPGA 的 PHOTON 哈希函数轻量级硬件架构


物联网 (IoT) 边缘设备和其他超轻量级设备的加密引擎设计是一项重大挑战。这种资源受限设备的出现对当前的密码算法提出了重大挑战。 PHOTON 是一种针对低资源设备的超轻量级加密哈希函数。目前实现的 PHOTON 哈希函数的硬件架构占用大量资源，工作频率低，吞吐量低。 PHOTON架构的最大工作频率和吞吐量可以提高，但代价是更大的面积利用率。因此，为了改善 PHOTON 哈希函数的面积性能权衡，本工作中实现了迭代架构。值得关注的是 PHOTON 哈希函数的最轻量级版本，其哈希大小为 80 位。它使用其综合和仿真工具在多个 Xilinx 和 Altera 现场可编程门阵列 (FPGA) 器件上实现和验证。低成本和高处理能力的 FPGA 器件都被考虑在内。该设计针对性能进行了优化，同时也考虑了面积利用率。整体性能和逻辑利用率以现有实现为基准。结果表明，与现有的 PHOTON 哈希函数实现相比，速度性能提高了 10.26% 至 51.04%，面积利用率降低了 7.55% 至 60.64%。