In this paper, a new 10-bit 1.2 GS/s hybrid digital to analog converter (DAC) simulated in 65 nm CMOS technology is presented. The new structure benefits from a combination of a resistor ladder and current sources. By using the resistor ladder, the identical current sources are weighted, which leads to remarkably reduce the number of current sources needed for realization a 10-bit DAC. Post layout simulation results indicate that the spurious-free dynamic range (SFDR) is more than 56 dB over 600 MHz Nyquist bandwidth. The INL and DNL parameters are also obtained better than 0.4 LSB. The proposed DAC dissipates just 7.49 mW power with a single supply voltage of 1.2 V. Also, the occupied area is 0.0071 mm².

本文提出了一种采用65 nm CMOS技术模拟的新型10位1.2 GS / s混合数模转换器（DAC）。新结构得益于电阻梯形图和电流源的组合。通过使用梯形电阻器，可以对相同的电流源进行加权，从而显着减少了实现10位DAC所需的电流源数量。布局后的仿真结果表明，在600 MHz的奈奎斯特带宽上，无杂散动态范围（SFDR）超过56 dB。还获得了优于0.4 LSB的INL和DNL参数。拟议的DAC在1.2 V的单电源电压下仅消耗7.49 mW的功率。此外，占用的面积为0.0071 mm ²。