This paper presents a reconfigurable frequency response masking (FRM) wideband channelizer architecture which is characterized by low computational and hardware complexity. The proposed hardware efficient architecture is realized by incorporating resource shared non-maximally decimated filter bank in the implementation of the FRM wideband channelizer structure. The coefficients of the proposed architecture are optimized and made multiplier-free using Pareto based meta-heuristic algorithm in the canonic signed digit (CSD) space for reducing the total power consumption of the architecture. The architecture is finally designed and synthesized using Xilinx Vivado and Cadence RTL Encounter compiler for the area and power analysis and is compared with existing channnelizer architectures. The comparison highlights the advantages of the proposed architecture in terms of hardware complexity, power and workload in realizing sharp wideband channel filters.

本文提出了一种可重配置的频率响应屏蔽（FRM）宽带信道器架构，该架构的特点是计算和硬件复杂度低。通过在FRM宽带信道器结构的实现中并入资源共享的非最大抽取滤波器组来实现所提出的硬件高效架构。在佳能符号数字（CSD）空间中，使用基于Pareto的元启发式算法对提出的体系结构的系数进行了优化，并使其无乘数，从而降低了体系结构的总功耗。最后，使用Xilinx Vivado和Cadence RTL Encounter编译器设计并综合了该体系结构，以进行面积和功耗分析，并将其与现有的通道发生器体系结构进行了比较。