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Self-Aligned Top-Gate Metal-Oxide Thin-Film Transistors Using a Solution-Processed Polymer Gate Dielectric
Micromachines ( IF 3.4 ) Pub Date : 2020-11-25 , DOI: 10.3390/mi11121035
Seungbeom Choi , Seungho Song , Taegyu Kim , Jae Cheol Shin , Jeong-Wan Jo , Sung Kyu Park , Yong-Hoon Kim

For high-speed and large-area active-matrix displays, metal-oxide thin-film transistors (TFTs) with high field-effect mobility, stability, and good uniformity are essential. Moreover, reducing the RC delay is also important to achieve high-speed operation, which is induced by the parasitic capacitance formed between the source/drain (S/D) and the gate electrodes. From this perspective, self-aligned top-gate oxide TFTs can provide advantages such as a low parasitic capacitance for high-speed displays due to minimized overlap between the S/D and the gate electrodes. Here, we demonstrate self-aligned top-gate oxide TFTs using a solution-processed indium-gallium-zinc-oxide (IGZO) channel and crosslinked poly(4-vinylphenol) (PVP) gate dielectric layers. By applying a selective Ar plasma treatment on the IGZO channel, low-resistance IGZO regions could be formed, having a sheet resistance value of ~20.6 kΩ/sq., which can act as the homojunction S/D contacts in the top-gate IGZO TFTs. The fabricated self-aligned top-gate IGZO TFTs exhibited a field-effect mobility of 3.93 cm2/Vs and on/off ratio of ~106, which are comparable to those fabricated using a bottom-gate structure. Furthermore, we also demonstrated self-aligned top-gate TFTs using electrospun indium-gallium-oxide (IGO) nanowires (NWs) as a channel layer. The IGO NW TFTs exhibited a field-effect mobility of 0.03 cm2/Vs and an on/off ratio of >105. The results demonstrate that the Ar plasma treatment for S/D contact formation and the solution-processed PVP gate dielectric can be implemented in realizing self-aligned top-gate oxide TFTs.

中文翻译:

使用溶液处理的聚合物栅极电介质的自对准顶栅金属氧化物薄膜晶体管

对于高速和大面积有源矩阵显示器,必不可少的是具有高场效应迁移率,稳定性和良好均匀性的金属氧化物薄膜晶体管(TFT)。此外,减小RC延迟对于实现高速操作也很重要,这是由源/漏(S / D)与栅电极之间形成的寄生电容引起的。从这个角度来看,由于S / D和栅电极之间的重叠最小,自对准顶栅氧化物TFT可以提供诸如高速显示器寄生电容低的优点。在这里,我们演示了使用溶液处理的铟镓锌氧化物(IGZO)通道和交联的聚(4-乙烯基苯酚)(PVP)栅极介电层的自对准顶栅氧化物TFT。通过对IGZO通道进行选择性Ar等离子体处理,可以形成低电阻IGZO区域,其薄层电阻值为〜20.6kΩ/ sq。,它可以用作顶栅IGZO TFT中的同质S / D接触。所制造的自对准顶栅IGZO TFT的场效应迁移率为3.93厘米2 / Vs和〜10 6的开/关比,与使用底栅结构制造的相比。此外,我们还演示了使用电纺氧化铟镓(IGO)纳米线(NWs)作为沟道层的自对准顶栅TFT。IGO NW TFT的场效应迁移率为0.03 cm 2 / Vs,通/断比> 10 5。结果表明,在实现自对准顶栅氧化物TFT时,可以实现S / D接触形成的Ar等离子体处理和固溶PVP栅介质。
更新日期:2020-11-25
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