Abstract We conducted experimental and quantitative studies on the effects of off-state bias stress of the p-type polycrystalline silicon thin film transistors, and present a degradation model using spatial mapping simulations. In the off-state bias stress condition, the gate induced drain leakage current (GIDL) is determined by the gate and drain voltage (Vgd), and the gate bias stress above a certain bias is accompanied by a change in Vth. The spatial distributions of the electric field and the electron concentration are considered as degradation factors, and are used in the equations for defect creation (DC) and the charge trapping (CT) model. We had to implement different forms of the aging model in the two regions: 1) CT in the poly-Si/SiOX interface, and 2) DC in the channel bulk. Finally, our degradation model allows us to analyze how the GIDL current decreases with various aging conditions, and provides a quantitative relationship between the amount of charge trapping and the amount of defect creation.

中文翻译：

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低温多晶硅薄膜晶体管老化关态偏置的空间映射退化建模

摘要 我们对 p 型多晶硅薄膜晶体管的断态偏置应力的影响进行了实验和定量研究，并提出了使用空间映射模拟的退化模型。在关态偏置应力条件下，栅极感应漏漏电流（GIDL）由栅极和漏极电压（Vgd）决定，高于一定偏置的栅极偏置应力伴随着Vth的变化。电场的空间分布和电子浓度被视为退化因素，并用于缺陷产生 (DC) 和电荷俘获 (CT) 模型的方程。我们必须在两个区域中实现不同形式的老化模型：1) 多晶硅/SiOX 界面中的 CT，以及 2) 通道体中的 DC。最后，