In this paper, 2 efficient reverse converters are introduced for the four-moduli set {2ⁿ⁻¹, 2ⁿ–1, 2ⁿ⁻¹–1, 2ⁿ⁺¹–1} which offers a high speed arithmetic unit due to its balanced modulus in the form of 2 ^k and 2 ^k–1. The proposed converters are designed in two-level architecture. ROM free and adder base structures are the advantages of the proposed converters which result in efficient implementation in VLSI circuits. New Chinese remainder theorem 1 (New CRT-I) and mixed radix conversion (MRC) algorithms are used to design the first and second proposed reverse converters, respectively. For the various dynamic ranges (DR), theoretical results based on unit gate model show that the proposed reverse converters have a better Area-Time (AT) metric in comparison to the reverse converters of the other similar four moduli set in the literature. Also based on FPGA implementation results,the proposed convertersoffer lower AT metric on average 12% and 10% when comparing with the latest design for similar the moduli set {2ⁿ, 2ⁿ⁺¹–1, 2ⁿ–1, 2ⁿ⁻¹–1}.