In this study, the influence of thermal budget on preparing hafnium silicate (HfSiO) and metal–insulator–semiconductor (MIS) structures with tetragonal hafnium oxide (HfO₂) films was investigated. Amorphous silicon (a-Si) was used as a sacrificial layer for HfSiO formation. Rapid thermal annealing (RTA) could efficiently drive the oxidation of a-Si with HfO₂. The RTA-produced HfSiO film thicker than that produced through furnace annealing could suppress gate leakage in MIS devices, and aid in maintaining a high dielectric constant of the gate insulator. The combination of sacrificial a-Si film use and RTA application resulted in a HfSiO/HfO₂ structure (named as hybrid HfO₂), which demonstrated a high dielectric constant and strength (29.5 and 21.2 MVcm⁻¹, respectively). MIS devices integrated with this hybrid HfO₂ achieved a hysteresis value of only 0.11V on a flat-band voltage measured at a 50mVs⁻¹ sweep rate with an applied voltage between −5 and 5V.

在这项研究中，研究了热预算对制备具有四方氧化铪 (HfO ₂ ) 薄膜的硅酸铪 (HfSiO) 和金属-绝缘体-半导体 (MIS) 结构的影响。非晶硅 (a-Si) 用作形成 HfSiO 的牺牲层。快速热退火 (RTA) 可以有效地驱动 a-Si 与 HfO ₂的氧化。RTA 生产的 HfSiO 薄膜比通过炉退火生产的薄膜厚，可以抑制 MIS 器件中的栅极泄漏，并有助于保持栅极绝缘体的高介电常数。牺牲 a-Si 膜的使用和 RTA 应用的结合导致了 HfSiO/HfO ₂结构（称为混合 HfO ₂)，显示出高介电常数和强度（分别为29.5 和 21.2 MVcm ^-1）。与这种混合 HfO ₂集成的 MIS 设备在以 50mVs ^-1扫描速率测量的平带电压上实现了仅为 0.11V 的滞后值，施加的电压介于 -5 和 5V 之间。