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Hardware Efficient Hybrid Encoder for Video Surveillance Application
Journal of Circuits, Systems and Computers ( IF 0.9 ) Pub Date : 2020-11-20 , DOI: 10.1142/s0218126621501139
Minesh Patel 1 , Anand Darji 1
Affiliation  

Extensive use of digital multimedia has led to the development of advance video processing techniques for development of multimedia applications. Application such as video surveillance requires 247 recording and streaming. So, the bandwidth and storage costs become significant. With introduction of video streaming over internet, where different kinds of end users request same content with different available bandwidth, it requires scalable video coding (SVC). These challenges can be overcome by developing new techniques to reduce redundancy in subsequent frames and to improve the coding efficiency. In this paper, overlapping weighted linear sum (OWLS) pre-processing method and its hardware architecture are proposed. It is implemented using field progrmmable gate array (FPGA) and the application specific integrated circuit (ASIC) is also developed using TSMC180nm technology standard cell library. Results show improvement in terms of power and area as compared to the existing work. In motion compensated temporal filtering (MCTF), wavelet transform is implemented by temporal filters. Architecture for 5/3 Lifting MCTF is also implemented and compared with baseline H.264 video codec. Simulation results show that the average peak signal to noise ratio (PSNR) improvement is 2.36dB. The MCTF design using 5/3 Lifting filter is synthesized for Virtex-5 FPGA and compared with the existing close-loop architecture with better performance.

中文翻译:

用于视频监控应用的硬件高效混合编码器

数字多媒体的广泛使用导致了用于开发多媒体应用的先进视频处理技术的发展。视频监控等应用需要 247 录制和流式传输。因此,带宽和存储成本变得非常重要。随着互联网视频流的引入,不同类型的最终用户请求具有不同可用带宽的相同内容,它需要可扩展视频编码 (SVC)。这些挑战可以通过开发新技术来减少后续帧中的冗余并提高编码效率来克服。本文提出了重叠加权线性和(OWLS)预处理方法及其硬件架构。它使用现场可编程门阵列 (FPGA) 实现,专用集成电路 (ASIC) 也使用 TSMC180nm 技术标准单元库开发。结果表明,与现有工作相比,功率和面积有所改善。在运动补偿时间滤波(MCTF)中,小波变换是通过时间滤波器实现的。还实现了 5/3 Lifting MCTF 架构,并与基线 H.264 视频编解码器进行了比较。仿真结果表明,平均峰值信噪比 (PSNR) 提升为 2.36 还实现了 5/3 Lifting MCTF 架构,并与基线 H.264 视频编解码器进行了比较。仿真结果表明,平均峰值信噪比 (PSNR) 提升为 2.36 还实现了 5/3 Lifting MCTF 架构,并与基线 H.264 视频编解码器进行了比较。仿真结果表明,平均峰值信噪比 (PSNR) 提升为 2.36D b。针对 Virtex-5 FPGA 综合了使用 5/3 Lifting 滤波器的 MCTF 设计,与现有闭环架构相比,性能更佳。
更新日期:2020-11-20
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