This paper presents a 32-GS/s front-end sampling circuit (FESC) in 65-nm CMOS. The FESC is designed for a 32-channel time-interleaved analog-to-digital converter (ADC), and the 4×8 two-stage interleaving structure leads to a good trade-off between bandwidth and linearity. The analysis and cancellation of charge injection, clock feedthrough, and signal feedthrough are presented. Inductor peaking technique is adopted to extend the bandwidth of the buffer between the first and the second stage. Based on the simulation results, the proposed FESC consumes 136mW at 32 GS/s, and the signal-to-noise ratio (SNDR) is up to 39.55 dB at Nyquist input, achieving a state-of-the-art power efficiency.

中文翻译：

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用于 65-nm CMOS 中的时间交错 ADC 的 32-GS/s 前端采样电路实现 >39 dB SNDR

本文介绍了 65-nm CMOS 中的 32-GS/s 前端采样电路 (FESC)。FESC 设计用于 32 通道时间交错模数转换器 (ADC)，并且4×8两级交织结构导致带宽和线性度之间的良好折衷。介绍了电荷注入、时钟馈通和信号馈通的分析和消除。采用电感峰化技术来扩展第一级和第二级之间缓冲器的带宽。根据仿真结果，提出的 FESC 消耗 13632 GS/s 时的 mW，奈奎斯特输入处的信噪比 (SNDR) 高达 39.55 dB，实现了最先进的功率效率。