In this paper, the impact of temperature and source/drain overlap on DC characteristics and analog/RF performance of the negative capacitance silicon nanotube FET (NC Si NTFET) have been presented. The performance of the device is examined by coupling the 3D TCAD numerical simulation with 1D Landau–Khalatnikov (LK) equation. The effect of negative capacitance has been investigated for different source/drain overlap lengths (${{\boldsymbol{L}}_{{\boldsymbol{ov}}}}$) at 300 K and 380 K. The optimal values of source/drain overlap lengths and effective ferroelectric thickness (${{\boldsymbol{t}}_{\boldsymbol{f}}}$) have been found to attain significant improvement in device performance in terms of drain current (${{\boldsymbol{I}}_{\boldsymbol{d}}}$), subthreshold swing (${\boldsymbol{SS}}$), gate capacitance (${{\boldsymbol{C}}_{\boldsymbol{g}}}$), and cut-off frequency (${{\boldsymbol{f}}_{\boldsymbol{t}}}$). It is reported that a minimum ${\boldsymbol{SS\ }}$of 30.7 mV/decade, and maximum ${{\boldsymbol{f}}_{\boldsymbol{t}}}$ of 2.35 THz are achieved for NC Si NTFET at 300 K for an operating frequency of 1 GHz. It is observed that the core (inner gate) radius ($t_c$) can be used to increase the minimum SS and I_ON to delay the hysteresis and to achieve a better drive current.

中文翻译：

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研究温度和源极/漏极重叠对负电容硅纳米管 FET (NC Si NTFET) 的影响，具有低于 60mV/decade 开关

本文介绍了温度和源极/漏极重叠对负电容硅纳米管 FET (NC Si NTFET) 的直流特性和模拟/射频性能的影响。通过将 3D TCAD 数值模拟与 1D Landau-Khalatnikov (LK) 方程耦合来检查设备的性能。已经针对不同的源极/漏极重叠长度研究了负电容的影响（${{\boldsymbol{L}}_{{\boldsymbol{ov}}}}$) 在 300 K 和 380 K. 源极/漏极重叠长度和有效铁电体厚度的最佳值 (${{\boldsymbol{t}}_{\boldsymbol{f}}}$) 已被发现可显着提高器件在漏极电流方面的性能 (${{\boldsymbol{I}}_{\boldsymbol{d}}}$), 亚阈值摆幅 (${\boldsymbol{SS}}$), 栅极电容 (${{\boldsymbol{C}}_{\boldsymbol{g}}}$) 和截止频率 (${{\boldsymbol{f}}_{\boldsymbol{t}}}$）。据悉，最低${\boldsymbol{SS\}}$30.7 mV/decade，最大值 ${{\boldsymbol{f}}_{\boldsymbol{t}}}$对于 300 K 的 NC Si NTFET，在 1 GHz 的工作频率下达到了 2.35 THz。据观察，核心（内浇口）半径（$t_c$) 可用于增加最小值 SS 和 我_开 以延迟滞后并获得更好的驱动电流。