This paper proposes a hardware implementation architecture for Fano decoding of polarization-adjusted convolutional (PAC) codes. This architecture maintains a trade-off between the error-correction performance and throughput of the decoder by setting a strict limit on its search complexity. The paper presents analyses of the complexity, combinational delay, and latency of the proposed architecture. The performance of the proposed decoder is evaluated on FPGA and ASIC using Xilinx Nexys 4 Artix-7 and TSMC 28 nm 0.72 V library, respectively. The PAC decoder can be clocked at 384.6 MHz and reach an information throughput of 9.34 MB/s at 3.5 dB signal-to-noise ratio for a block length of 128 and code rate of 1/2.

中文翻译：

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PAC 码 Fano 解码器的硬件实现

本文提出了一种用于极化调整卷积 (PAC) 码的 Fano 解码的硬件实现架构。该架构通过对其搜索复杂度设置严格限制，在解码器的纠错性能和吞吐量之间保持平衡。本文对所提出架构的复杂性、组合延迟和延迟进行了分析。所提出的解码器的性能分别使用 Xilinx Nexys 4 Artix-7 和 TSMC 28 nm 0.72 V 库在 FPGA 和 ASIC 上进行评估。PAC 解码器的时钟频率为 384.6 MHz，在 3.5 dB 信噪比下，对于 128 块长度和 1/2 码率，信息吞吐量可达到 9.34 MB/s。