We present an extensive investigation of the charge-trapping processes in vertical GaN nanowire FETs with a gate-all-around structure. Two sets of devices were investigated: Gen1 samples have unipolar (n-type) epitaxy, whereas Gen2 samples have a p-doped channel and an n-p-n gate stack. From experimental results, we demonstrate the superior performance of the transistor structure with a p-GaN channel/Al2O3 gate insulator in terms of dc performance. In addition, we demonstrate that Gen2 devices have highly stable threshold voltage, thus representing ideal devices for power electronic applications. Insight into the trapping processes in the two generations of devices was obtained by modeling the threshold voltage variations via differential rate equations.

中文翻译：

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GaN 纳米线 FET 中高度稳定的阈值电压：p-GaN 沟道/Al2O3 栅极绝缘体的优势

我们对具有环栅结构的垂直 GaN 纳米线 FET 中的电荷俘获过程进行了广泛的研究。研究了两组器件：Gen1 样品具有单极（n 型）外延，而 Gen2 样品具有 p 掺杂沟道和 npn 栅极堆叠。根据实验结果，我们证明了具有 p-GaN 沟道/Al2O3 栅极绝缘体的晶体管结构在直流性能方面的优越性能。此外，我们证明了 Gen2 器件具有高度稳定的阈值电压，因此是电力电子应用的理想器件。通过微分速率方程对阈值电压变化进行建模，可以深入了解两代器件中的俘获过程。