Processor design validation and debug is a difficult and complex task, which consumes the lion's share of the design process. Design bugs that affect processor performance rather than its functionality are especially difficult to catch, particularly in new microarchitectures. This is because, unlike functional bugs, the correct processor performance of new microarchitectures on complex, long-running benchmarks is typically not deterministically known. Thus, when performance benchmarking new microarchitectures, performance teams may assume that the design is correct when the performance of the new microarchitecture exceeds that of the previous generation, despite significant performance regressions existing in the design. In this work, we present a two-stage, machine learning-based methodology that is able to detect the existence of performance bugs in microprocessors. Our results show that our best technique detects 91.5% of microprocessor core performance bugs whose average IPC impact across the studied applications is greater than 1% versus a bug-free design with zero false positives. When evaluated on memory system bugs, our technique achieves 100% detection with zero false positives. Moreover, the detection is automatic, requiring very little performance engineer time.

中文翻译：

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自动微处理器性能缺陷检测

处理器设计验证和调试是一项艰巨而复杂的任务，它占用了设计过程的大部分时间。影响处理器性能而非功能的设计错误特别难以捕捉，尤其是在新的微体系结构中。这是因为，与功能错误不同，新微架构在复杂、长期运行的基准测试中的正确处理器性能通常是不确定的。因此，在对新微架构进行性能基准测试时，尽管设计中存在显着的性能回归，但当新微架构的性能超过上一代时，性能团队可能会假设设计是正确的。在这项工作中，我们提出了一个两个阶段，基于机器学习的方法，能够检测微处理器中是否存在性能错误。我们的结果表明，我们的最佳技术检测到 91.5% 的微处理器内核性能错误，与零误报的无错误设计相比，这些错误对所研究的应用程序的平均 IPC 影响大于 1%。当对内存系统错误进行评估时，我们的技术实现了 100% 的检测和零误报。此外，检测是自动的，只需要很少的性能工程师时间。我们的技术实现了 100% 检测，零误报。此外，检测是自动的，只需要很少的性能工程师时间。我们的技术以零误报实现了 100% 检测。此外，检测是自动的，只需要很少的性能工程师时间。