The notion of recurrence over continuous or dense time, as required for expressing Analog and Mixed-Signal (AMS) behaviours, is fundamentally different from what is offered by the recurrence operators of SystemVerilog Assertions (SVA). This article introduces the formal semantics of recurrence over dense time and provides a methodology for the runtime verification of such properties using interval arithmetic. Our property language extends SVA with dense real-time intervals and predicates containing real-valued signals. We provide a tool kit which interfaces with off-the-shelf EDA tools through standard VPI.

中文翻译：

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密集时间 AMS 断言中的重复出现

表达模拟和混合信号 (AMS) 行为所需的连续或密集时间的递归概念与 SystemVerilog 断言 (SVA) 的递归运算符所提供的概念根本不同。本文介绍了密集时间内递归的形式语义，并提供了一种使用区间算法对此类属性进行运行时验证的方法。我们的属性语言使用密集的实时间隔和包含实值信号的谓词扩展了 SVA。我们提供了一个工具包，它通过标准 VPI 与现成的 EDA 工具连接。