In this paper, bulk CMOS finFET, horizontal gate-all-around (GAA) nanowire and nanosheet field-effect transistors are compared for the 5 ​nm technology node. The performance of these transistors and the circuits comprising them is assessed through 3-D technology computer-aided design (TCAD) simulations and circuit level SPICE simulations of BSIM compact models calibrated to the TCAD results, respectively. Full parasitic extraction is used on standard cell and static random access (SRAM) memory cell layouts to ensure accurate delays. The target of this work is a 5 ​nm technology node follow-on to an existing 7 ​nm predictive process design kit (PDK) in common academic use. Subthreshold slope, drain induced barrier lowering, gate-induced drain leakage and subthreshold current are compared for different gate lengths. Transistor performance is also compared for various raised source/drain lengths and low-k gate spacer widths. The gate-all-around field-effect transistors show better electrostatic performance as expected. However, the simulation results show that finFET devices will be adequate at the 5 ​nm node, should the GAA devices prove to be difficult to produce in high volume manufacturing.

本文针对5 nm技术节点比较了体CMOS finFET，水平全栅（GAA）纳米线和纳米片场效应晶体管。这些晶体管及其电路的性能分别通过3-D技术计算机辅助设计（TCAD）仿真和根据TCAD结果校准的BSIM紧凑型模型的电路级SPICE仿真进行评估。在标准单元和静态随机存取（SRAM）存储单元布局上使用完全寄生提取，以确保准确的延迟。这项工作的目标是在学术界普遍使用的现有7纳米预测性工艺设计套件（PDK）的后续5纳米技术节点。比较了不同栅极长度的亚阈值斜率，漏极引起的势垒降低，栅极引起的漏极泄漏和亚阈值电流。还比较了各种提高的源极/漏极长度和低k栅极隔离层宽度的晶体管性能。环绕栅场效应晶体管具有预期的更好的静电性能。但是，仿真结果表明，如果证明GAA器件难以在大批量生产中生产，finFET器件将在5 nm节点上足够使用。