An efficient Fast logarithmic successive cancellation stack (Log-SCS) polar decoding algorithm is proposed along with its software implementation using single instruction multiple data (SIMD) style processing. Quantitatively, we reduce the decoding complexity by 50% on average, while simultaneously attaining a decoding latency that is only 21% of that of the state-of-the-art Fast successive cancellation list (SCL) polar decoder's software implementation. This is achieved without any loss of error correction performance by applying simplified path-metric (PM) computations for the rate-0, rate-1 and repetition sub-graphs of the proposed Fast Log-SCS decoder. Furthermore, a software implementation of the 32-bit fixed-point Fast Log-SCS polar decoder is conceived for x86 processors, which maintains the same block error ratio (BLER) as the floating-point Log-SCS polar decoder. Additionally, our software implementation is accelerated using SIMD instructions by relying on 512-bit Advanced Vector Extensions (AVX-512) and recursive template meta-programming for the first time, achieving a parallelism of 16, which makes it eminently suitable for the low-latency requirements of software-defined radio systems.

中文翻译：

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用于 5G 新无线电的复杂度降低的低延迟对数连续消除堆栈极性解码及其软件实现


提出了一种高效的快速对数连续消除堆栈 (Log-SCS) 极性解码算法及其使用单指令多数据 (SIMD) 样式处理的软件实现。从数量上来说，我们将解码复杂度平均降低了 50%，同时解码延迟仅为最先进的快速连续消除列表 (SCL) 极性解码器软件实现的 21%。这是通过对所提出的快速 Log-SCS 解码器的速率 0、速率 1 和重复子图应用简化的路径度量 (PM) 计算来实现的，不会损失任何纠错性能。此外，还为 x86 处理器设计了 32 位定点快速 Log-SCS 极性解码器的软件实现，它保持与浮点 Log-SCS 极性解码器相同的块错误率 (BLER)。此外，我们的软件实现通过SIMD指令进行加速，首次依靠512位高级矢量扩展（AVX-512）和递归模板元编程，实现了16的并行度，这使得它非常适合低功耗软件定义无线电系统的延迟要求。