Abstract Given the importance of reducing energy consumption and the challenge of heat generation in classic CMOS circuits, adiabatic circuits are believed as an appropriate alternative. Most of the adiabatic circuit families come with a dual-rail structure, which provides them with an inherent hardware redundancy. Although this redundancy could be used for improving their reliability, no studies have been previously conducted to exploit this feature. In this regard, in this paper, we show that by exploiting the inherent hardware redundancy in adiabatic circuits, their reliability could be improved, while imposing a relatively low amount of energy overhead. Subsequently, with utilizing the outcome observations, we have proposed LWRAP, a fault tolerant circuit design for dual-rail adiabatic families. While improving the reliability, LWRAP employs the well-known dynamic frequency scaling approach for mitigating the amount of imposed energy overhead in the design. Our precise SPICE simulations have shown that LWRAP improves the reliability of the circuit against transient faults by up to 12x, depending on the technology size.

中文翻译：

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低浪费、可靠的绝热平台

摘要 鉴于经典 CMOS 电路中降低能耗的重要性和发热的挑战，绝热电路被认为是一种合适的替代方案。大多数绝热电路系列都带有双轨结构，这为它们提供了固有的硬件冗余。尽管这种冗余可用于提高它们的可靠性，但之前没有研究利用此功能。在这方面，在本文中，我们表明，通过利用绝热电路中固有的硬件冗余，可以提高它们的可靠性，同时施加相对较低的能量开销。随后，利用观察结果，我们提出了 LWRAP，一种用于双轨绝热系列的容错电路设计。在提高可靠性的同时，LWRAP 采用众所周知的动态频率缩放方法来减少设计中施加的能量开销。我们精确的 SPICE 仿真表明，LWRAP 可将电路针对瞬态故障的可靠性提高多达 12 倍，具体取决于技术规模。