In this paper, we report a junctionless FinFET-based capacitor less dynamic memory by using three-dimensional technology computer-aided design simulations. To realize the 1T-DRAM, the proposed device has been designed as a structure in which a poly-si layer is deposited on the fins of a typical junctionless FinFET. Poly-si has one or more grain boundaries (GB). A GB contains multiple traps, and these traps generally degrade device performance. Also, when poly-si is grown and utilized in semiconductor devices, non-uniform GB is formed across the entire wafer. Therefore, devices manufactured using poly-si have different GBs for each device and the performance of devices fabricated on the same wafer is different. Therefore, it is essential to design a device that can operate normally regardless of GB. The 1T-DRAM proposed in this study was simulated with the existence of GB and the direction of GB differently. Finally, a device that operates normal memory regardless of GB was designed. According to the simulation results, the retention time of the proposed 1T-DRAM has a margin of more than 10 uA/um and a retention time of more than 64 ms, regardless of the presence or absence of GBs.

中文翻译：

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使用多晶硅晶界模拟基于无结 FinFET 的无电容动态随机存取存储器

在本文中，我们通过使用三维技术计算机辅助设计模拟，报告了一种基于无结 FinFET 的无电容动态存储器。为了实现 1T-DRAM，所提出的器件被设计为一种结构，其中多晶硅层沉积在典型的无结 FinFET 的鳍上。多晶硅具有一个或多个晶界 (GB)。GB 包含多个陷阱，这些陷阱通常会降低设备性能。此外，当多晶硅生长并用于半导体器件时，会在整个晶片上形成不均匀的 GB。因此，使用poly-si 制造的器件对于每个器件具有不同的GB，并且在同一晶片上制造的器件的性能不同。因此，设计一种无论GB如何都可以正常运行的设备至关重要。本研究中提出的 1T-DRAM 是在 GB 的存在和 GB 的方向不同的情况下进行模拟的。最后，设计了一种无论 GB 大小都可以运行正常内存的设备。根据仿真结果，无论是否存在 GB，所提出的 1T-DRAM 的保留时间都具有超过 10 uA/um 的余量和超过 64 ms 的保留时间。