This work proposes a mathematical delay models for global VLSI interconnects using normalized asymptotic value of characteristic impedance of RLC interconnected line. In the proposed Model (R₀C₀) the delay of RLC interconnects line is formulated by incorporating the line inductance in terms of effective impedance. The earlier simple RC interconnect models results in a significant error in delay estimation in long interconnects. Due to this analogy the non-ideal effect of inductive behaviour at high frequencies and scaled technologies such as ringing, spikes overshoot and undershoot can be suppressed. The dominance of inductance effect is optimized by Simulative Sweep Analysis Techniques (SSAT). Accuracy is verified by analytical and SPICE simulation results. Step response analysis of the proposed model is validated with the existing literature and found to be superior. Using this approach the results for both the signaling technique i.e. voltage and current mode signaling are found in close agreement between analytical and simulation for long interconnect lines.

这项工作使用RLC互连线的特征阻抗的归一化渐近值，为全球VLSI互连提出了一个数学延迟模型。在建议的模型中（R ₀ C ₀）RLC互连线路的延迟是通过将线路电感纳入有效阻抗来制定的。早期的简单RC互连模型会导致长互连中延迟估计的重大误差。由于这种类比，可以抑制高频下的电感行为和诸如振铃，尖峰过冲和下冲之类的缩放技术的非理想影响。通过模拟扫描分析技术（SSAT）优化了电感效应的优势。通过分析和SPICE仿真结果验证了准确性。所提出模型的阶跃响应分析已在现有文献中得到验证，并且被认为是更好的。使用这种方法，两种信令技术的结果，即