A SiC trench MOSFET with an enhanced vertical RESURF effect is proposed and analyzed in this article. The device features a deep oxide trench surrounded by a P-type doping layer at the source-side. With the assistant depletion effect of the P-type layer, the concentration of the N-drift region is increased and the specific on-resistance ( ${R} _{\mathrm{ on,sp}}$ ) is thus reduced. The P-type doping can significantly reduce the intensity of the electric field at the gate oxide corner, and modulate the bulk electric field for the device. The breakdown voltage (BV) is therefore improved. As a result, the proposed SiC MOSFET has a better trade-off of BV and ${R} _{\mathrm{ on,sp}}$ . The ${R} _{\mathrm{ on,sp}}$ decreases by 59% and the BV increases by 16% for the proposed device without a CSL layer compared with the conventional trench MOSFET with a CSL layer. Meanwhile, the device exhibits a lower gate-to-drain charge ( ${Q} _{\mathrm{ gd}}$ ) which is reduced by 52% and the switching loss is also reduced by 19%.

中文翻译：

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具有增强垂直RESURF效应的1200V SiC沟槽MOSFET的仿真研究

本文提出并分析了一种具有增强型垂直 RESURF 效应的 SiC 沟槽 MOSFET。该器件具有一个深氧化沟槽，在源极侧被 P 型掺杂层包围。在 P 型层的辅助耗尽作用下，N 漂移区的浓度增加，比导通电阻 ( ${R} _{\mathrm{ on,sp}}$ ) 因而减少。P型掺杂可以显着降低栅氧化角处的电场强度，并调制器件的体电场。击穿电压（BV) 因此得到改进。因此，所提出的 SiC MOSFET 在 BV 和 ${R} _{\mathrm{ on,sp}}$ . 这 ${R} _{\mathrm{ on,sp}}$ 减少了 59% 并且 BV与具有 CSL 层的传统沟槽 MOSFET 相比，没有 CSL 层的拟议器件增加了 16%。同时，该器件表现出较低的栅漏电荷（ ${Q} _{\mathrm{ gd}}$ ) 降低了 52%，开关损耗也降低了 19%。