This paper exhibits a word-serial unified and scalable semi-systolic processor core for concurrently executing both multiplication and squaring operations over GF($2^k$). The processor is extracted by applying a chosen non-linear scheduling and projection functions to the dependency graph of the adopted bipartite multiplication-squaring algorithm. It has the advantage of sharing the data-path resources between the two operations leading to considerable savings in both space and power resources. Also, the processor’s scalability nature provides the designer with higher flexibility to manage the processor size as well as its execution time. The acquired ASIC synthesis results of the explored word-serial multiplier-squarer architecture and the reported competing word-serial multiplier architectures indicate that the developed design significantly outperforms the competing ones in terms of area and consumed energy at the word-size of 32-bits. Therefore, the explored architecture is more suited for realizing cryptographic primitives in all resource-constrained embedded applications operating at this word-size.

本文展示了一种字串行统一可扩展的半收缩处理器内核，可同时在GF（）上执行乘法和平方运算$2^{ķ}$）。通过将选定的非线性调度和投影函数应用于所采用的二部乘-平方算法的依赖图，可以提取处理器。它具有在两个操作之间共享数据路径资源的优势，从而节省了空间和功率资源。而且，处理器的可扩展性为设计人员提供了更大的灵活性来管理处理器尺寸及其执行时间。所探索的字串行乘方平方架构和所报告的竞争字串行乘数架构的ASIC综合结果表明，在32位字长的情况下，所开发的设计在面积和能耗方面明显优于竞争产品。 。因此，