A novel modification in the evanescent mode analysis is presented in this work to comprehend the implication of a high gate dielectric constant in the subthreshold model of junctionless (JL) asymmetric double gate (DG) FETs. A brief study is presented to highlight the lack of an appropriate device model for the JL FET with a sub-1 nm equivalent oxide thickness. This work elaborates the effect of a high-k gate dielectric on one of the most important parameters of evanescent mode analysis, known as the inverse characteristics length. Thereby, an appropriate modification is incorporated in the widely adopted evanescent mode analysis to develop the subthreshold model compatible with high-k gate-dielectric materials and sub-1 nm gate-oxide thickness. Subsequently, the subthreshold model of DG FET with a high-k gate dielectric is presented. The DG FET assumes gate-oxide asymmetry as well as channel doping asymmetry arising due to the ion-implantation and subsequent annealing. With the help of the developed model, the subthreshold characteristics of the device are studied with the variations in device dimensions, the gate-dielectric constant, the doping profile, etc. The results have been found to be in good agreement when numerically studied in comparison with the outcomes of the Synopsys Sentaurus™ Device simulation tool.

在这项工作中提出了一种在the逝模式分析中的新颖修改，以理解高结介电常数在无结（JL）非对称双栅（DG）FET的亚阈值模型中的含义。提出了一项简短的研究，以突出显示缺乏等效氧化物厚度小于1 nm的JL FET的合适器件模型。这项工作阐述了高k栅极电介质对渐逝模式分析的最重要参数之一（称为反特性长度）的影响。因此，在广泛采用的渐逝模式分析中加入了适当的修改，以开发与高k兼容的亚阈值模型。栅介电材料和1 nm以下的栅氧化层厚度。随后，提出了具有高k栅极电介质的DG FET的亚阈值模型。DG FET假定由于离子注入和随后的退火而产生的栅极氧化物不对称以及沟道掺杂不对称。借助开发的模型，研究了器件的亚阈值特性，包括器件尺寸，栅极介电常数，掺杂分布等的变化。通过比较研究数值，发现结果具有很好的一致性。带有Synopsys Sentaurus™设备仿真工具的结果。