This study presents a high boost DC–DC converter, integrates voltage multiplier cell, voltage lift capacitor, and coupled-inductor techniques to achieve a high-voltage gain. The proposed topology has the capability of extension without utilising any additional winding for a very large voltage conversion ratio. With utilising a passive clamp circuit and without requiring higher duty cycle values, the suggested converter obtains a large conversion ratio, low conduction losses, and reduced voltage stress of semiconductors with a steady value for the whole range of duty cycle. The converter operation principle is discussed and its steady-state operation is analysed in detail. Also, theoretic efficiency calculation and design guidelines of the topology are explained. Then, the proposed DC–DC converter is compared with similar configurations to indicate its advantages. Eventually, the validity of theoretic analysis is verified using experimental measurement results of the implemented prototype with a power rating of 226 W.

中文翻译：

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具有大转换比和减小半导体上的电压应力的耦合电感器DC-DC转换器的拓扑

这项研究提出了一种高升压DC-DC转换器，它集成了倍压单元，升压电容器和耦合电感器技术以实现高电压增益。所提出的拓扑具有扩展能力，而无需利用任何额外的绕组来获得非常大的电压转换比。通过使用无源钳位电路，并且不需要较高的占空比值，建议的转换器在整个占空比范围内具有稳定值的情况下，可获得较大的转换比，较低的导通损耗并降低了半导体的电压应力。讨论了转换器的工作原理，并详细分析了其稳态工作。此外，还解释了拓扑的理论效率计算和设计指南。然后，建议的DC-DC转换器与类似配置进行比较，以表明其优势。最终，使用已实现的原型的额定功率为226 W的实验测量结果验证了理论分析的有效性。