Resistive Random Access Memory (RRAM) based Physical Unclonable Function (PUF) designs exploit either the probabilistic switching or the resistance variability during forming, SET and RESET processes of RRAM. Memory PUFs using RRAM are typically weak PUFs due to fewer number of challenge response pairs. We propose a strong arbiter PUF based on 1T-1R bit cell which is designed from conventional RRAM memory array with minimally invasive changes. Conventional voltage sense amplifier is repurposed to act like an arbiter and generate the response. Similarly, address and data lines are repurposed to act as challenge and response bits respectively. The PUF is simulated using 65 nm predictive technology models for CMOS and Verilog-A model for a hafnium oxide based RRAM. The proposed PUF architecture is evaluated for uniqueness, uniformity and reliability for various number of stages. It demonstrates mean intra-die Hamming Distance (HD) of 0.135 percent and inter-die HD of 51.4 percent, and passes the NIST tests. We study the vulnerability of proposed PUF to machine learning attacks. We also present an application of proposed PUF for data attestation in the internet of things. Proposed PUF-based data attestation consumes 9.88pJ of total energy per data block of 64-bits and offers a speed of 120.7 kbps.

中文翻译：

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基于嵌入式电阻RAM的强仲裁器PUF的设计、分析与应用

基于电阻随机存取存储器 (RRAM) 的物理不可克隆功能 (PUF) 设计利用 RRAM 的形成、设置和重置过程中的概率切换或电阻可变性。由于质询响应对的数量较少，使用 RRAM 的内存 PUF 通常是弱 PUF。我们提出了一种基于 1T-1R 位单元的强仲裁 PUF，它是从传统的 RRAM 存储器阵列设计的，具有微创的变化。传统的电压检测放大器被重新用作仲裁器并产生响应。类似地，地址线和数据线分别用作质询和响应位。PUF 使用 65 nm 预测技术模型进行仿真，用于 CMOS 和 Verilog-A 模型用于基于氧化铪的 RRAM。建议的 PUF 架构进行了唯一性评估，不同阶段的一致性和可靠性。它表明平均芯片内汉明距离 (HD) 为 0.135%，芯片间 HD 为 51.4%，并通过了 NIST 测试。我们研究了提议的 PUF 对机器学习攻击的脆弱性。我们还提出了建议的 PUF 在物联网数据证明中的应用。提议的基于 PUF 的数据证明每 64 位数据块消耗 9.88pJ 的总能量，并提供 120.7 kbps 的速度。