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FPGA-based Hyrbid Memory Emulation System
arXiv - CS - Hardware Architecture Pub Date : 2020-11-09 , DOI: arxiv-2011.04567
Fei Wen, Mian Qin, Paul V. Gratz, A.L.Narasimha Reddy

Hybrid memory systems, comprised of emerging non-volatile memory (NVM) and DRAM, have been proposed to address the growing memory demand of applications. Emerging NVM technologies, such as phase-change memories (PCM), memristor, and 3D XPoint, have higher capacity density, minimal static power consumption and lower cost per GB. However, NVM has longer access latency and limited write endurance as opposed to DRAM. The different characteristics of two memory classes point towards the design of hybrid memory systems containing multiple classes of main memory. In the iterative and incremental development of new architectures, the timeliness of simulation completion is critical to project progression. Hence, a highly efficient simulation method is needed to evaluate the performance of different hybrid memory system designs. Design exploration for hybrid memory systems is challenging, because it requires emulation of the full system stack, including the OS, memory controller, and interconnect. Moreover, benchmark applications for memory performance test typically have much larger working sets, thus taking even longer simulation warm-up period. In this paper, we propose a FPGA-based hybrid memory system emulation platform. We target at the mobile computing system, which is sensitive to energy consumption and is likely to adopt NVM for its power efficiency. Here, because the focus of our platform is on the design of the hybrid memory system, we leverage the on-board hard IP ARM processors to both improve simulation performance while improving accuracy of the results. Thus, users can implement their data placement/migration policies with the FPGA logic elements and evaluate new designs quickly and effectively. Results show that our emulation platform provides a speedup of 9280x in simulation time compared to the software counterpart Gem5.

中文翻译:

基于FPGA的混合内存仿真系统

由新兴的非易失性存储器 (NVM) 和 DRAM 组成的混合存储器系统已被提议用于解决应用程序不断增长的存储器需求。相变存储器 (PCM)、忆阻器和 3D XPoint 等新兴 NVM 技术具有更高的容量密度、最小的静态功耗和更低的每 GB 成本。然而,与 DRAM 相比,NVM 具有更长的访问延迟和有限的写入耐久性。两种存储器类别的不同特征指向包含多个主存储器类别的混合存储器系统的设计。在新架构的迭代和增量开发中,仿真完成的及时性对于项目进展至关重要。因此,需要一种高效的仿真方法来评估不同混合存储系统设计的性能。混合内存系统的设计探索具有挑战性,因为它需要模拟整个系统堆栈,包括操作系统、内存控制器和互连。此外,用于内存性能测试的基准应用程序通常具有更大的工作集,因此需要更长的模拟预热期。在本文中,我们提出了一种基于 FPGA 的混合内存系统仿真平台。我们的目标是移动计算系统,它对能源消耗很敏感,并且可能会采用 NVM 以提高其能效。在这里,因为我们平台的重点是混合内存系统的设计,所以我们利用板载硬核 IP ARM 处理器来提高仿真性能,同时提高结果的准确性。因此,用户可以使用 FPGA 逻辑元件实施他们的数据放置/迁移策略,并快速有效地评估新设计。结果表明,与软件对应的 Gem5 相比,我们的仿真平台在仿真时间上提供了 9280 倍的加速。
更新日期:2020-11-10
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