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Hardware‐efficient approximate logarithmic division with improved accuracy
International Journal of Circuit Theory and Applications ( IF 1.8 ) Pub Date : 2020-11-09 , DOI: 10.1002/cta.2900
Chitlu Subhasri 1 , Bhaskara Rao Jammu 1 , L. Guna Sekhar Sai Harsha 1 , Nalini Bodasingi 2 , Visweswara Rao Samoju 1
Affiliation  

Among all the arithmetic operations, division operation takes most of the clock cycles resulting in more path delay and higher power consumption. Many algorithms, including logarithmic division (LD), have been implemented to reduce the critical path delay and power consumption of division operation. However, there is a high possibility to further reduce these vital issues by using the novel approximate LD (ALD) algorithm. In the proposed ALD, a truncation adder is used for mantissa addition. Using this adder, the power delay product (PDP) and normalized mean error distance (NMED) are minimized. From the error analysis and hardware evaluation, it is observed that the proposed ALD using truncation adder (ALD‐TA) with an appropriate number of inexact bits achieve lower power consumption and higher accuracy than existing LDs with exact units. The normalized mean error distance of 8‐, 16‐, and 32‐bit ALD‐TA is compared with LDs of same bits and observed a decrease of up to 21%, 20%, and 21%, and the PDP has a reduction of up to 33%, 51%, and 72%, respectively. Application of ALD‐TA to image processing shows that high performance can be achieved by using ALDs than exact LDs.

中文翻译:

硬件有效的近似对数除法,提高了精度

在所有算术运算中除法运算占用大多数时钟周期,从而导致更多的路径延迟和更高的功耗。已经实现了许多算法,包括对数除法(LD),以减少关键路径延迟和除法运算的功耗。但是,通过使用新颖的近似LD(ALD)算法,很有可能进一步减少这些重要问题。在提出的ALD中,截断加法器用于尾数加法。使用该加法器,可以将功率延迟乘积(PDP)和归一化平均误差距离(NMED)降至最小。从错误分析和硬件评估中可以看出,与具有精确单位的现有LD相比,使用具有适当数量的不精确位的截断加法器(ALD-TA)提出的ALD可以实现更低的功耗和更高的精度。归一化平均误差距离为8‐ 将16位和32位ALD-TA与相同位的LD进行比较,观察到最多减少了21%,20%和21%,而PDP最多减少了33%,51%和分别为72%。ALD-TA在图像处理中的应用表明,与精确的LD相比,使用ALD可以实现高性能。
更新日期:2021-01-15
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