Low-voltage-triggered silicon-controlled rectifier (LVTSCR) is expected to provide an electrostatic discharge (ESD) protection for a low-voltage integrated circuit. However, it is normally vulnerable to the latch-up effect due to its extremely low holding voltage. In this paper, a novel LVTSCR embedded with an extra p-type MOSFET called EP-LVTSCR has been proposed and verified in a 28-nm CMOS technology. The proposed device possesses a lower trigger voltage of ~ 6.2 V and a significantly higher holding voltage of ~ 5.5 V with only 23% degradation of the failure current under the transmission line pulse test. It is also shown that the EP-LVTSCR operates with a lower turn-on resistance of ~ 1.8 Ω as well as a reliable leakage current of ~ 1.8 nA measured at 3.63 V, making it suitable for ESD protections in 2.5 V/3.3 V CMOS processes. Moreover, the triggering mechanism and conduction characteristics of the proposed device were explored and demonstrated with TCAD simulation.

低压触发可控硅（LVTSCR）有望为低压集成电路提供静电放电（ESD）保护。但是，由于其极低的保持电压，通常容易受到闩锁效应的影响。在本文中，提出了一种新颖的LVTSCR，该LVTSCR嵌入了一个称为EP-LVTSCR的额外p型MOSFET，并已通过28 nm CMOS技术进行了验证。所提出的器件具有较低的触发电压（约6.2 V）和较高的保持电压（约5.5 V），并且在传输线脉冲测试下故障电流仅降低了23％。还表明，EP-LVTSCR的开通电阻较低，约为〜1.8Ω，在3.63 V时测得的可靠泄漏电流约为〜1.8 nA，使其适用于2.5 V / 3.3 V CMOS的ESD保护。流程。此外，