CMOS analog and mixed-signal phase-locked loops (PLL) are widely used in varies of the system-on-chips (SoC) as the clock generator or frequency synthesizer. This paper presents an overview of the AMS-PLL, including: 1) a brief introduction of the basics of the charge-pump based PLL, which is the most widely used AMS-PLL architecture due to its simplicity and robustness; 2) a summary of the design issues of the basic CPPLL architecture; 3) a systematic introduction of the techniques for the performance enhancement of the CPPLL; 4) a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter (< 100 fs) with lower power consumption compared with the CPPLL, including the injection-locked PLL (ILPLL), sub-sampling (SSPLL) and sampling PLL (SPLL); 5) a discussion about the consideration of the AMS-PLL architecture selection, which could help designers meet their performance requirements.

中文翻译：

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CMOS 模拟和混合信号锁相环：概述

CMOS 模拟和混合信号锁相环 (PLL) 广泛用于各种片上系统 (SoC) 作为时钟发生器或频率合成器。本文介绍了 AMS-PLL 的概述，包括：1) 简要介绍了基于电荷泵的 PLL 的基础知识，它是最广泛使用的 AMS-PLL 架构，因为它的简单性和鲁棒性；2）基本CPPLL架构的设计问题总结；3) CPPLL性能提升技术的系统介绍；4) 超低抖动 AMS-PLL 架构的简要概述，与 CPPLL 相比，可以实现更低抖动 (< 100 fs) 和更低功耗，包括注入锁定 PLL (ILPLL)、子采样 (SSPLL)和采样锁相环（SPLL）；