Nanosheet field-effect transistors (NSFETs) have emerged as a novel device replacement for sub-7nm CMOS technology nodes. However, due to smaller fin thickness (Tfin = 5nm), NSFETs are more vulnerable to the process-induced variations. Among various types of process-induced variations, Line edge roughness (LER) is becoming a significant concern for multi-gate field-effect transistors (MugFETs) with smaller feature sizes. In this article, we have reported and compared the impact of LER on the electrical characteristics of NSFETs and nanowire field-effect transistors (NWFETs) for the sub-7nm technology node. We have generated a 3-D LER profile using 2-D Auto Covariance Function (ACVF) that considers two degrees of freedom for a realistic roughness analysis at advanced CMOS technology nodes. For a complete study of 3-D LER effect in NSFET, we have considered roughness along the nanosheet’s sidewalls as well as top and bottom surfaces. We have shown using 3D TCAD simulations that the sidewall roughness in NSFETs contributes to a negligible mismatch in threshold voltage and ON current. The mismatch performance of NSFET is compared with that of the NWFET for sub-7nm technology node. NSFET appears to be more immune to mismatch in ON current than NWFETs considered in this work. On the other hand, as compared with NSFET, owing to its superior gate all-around control, the NWFET achieves lower mismatch in drain induced barrier lowering (DIBL) and subthreshold slope (SS) in presence of LER. In addition to this, FETs with different channel doping modes such as inversion (IM) and Junction less (JL) mode have been compared for their matching performance against 3-D LER. It can be concluded from the results that IM FETs are more immune to 3-D LER as compared to JL FETs.

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5-nm CMOS 的 NWFET 和 NSFET 中 LER 诱导失配的比较

纳米片场效应晶体管 (NSFET) 已成为亚 7 纳米 CMOS 技术节点的新型器件替代品。然而，由于鳍片厚度较小（Tfin = 5nm），NSFET 更容易受到工艺引起的变化的影响。在各种类型的工艺引起的变化中，线边缘粗糙度 (LER) 正成为具有较小特征尺寸的多栅场效应晶体管 (MugFET) 的一个重要问题。在本文中，我们报告并比较了 LER 对亚 7nm 技术节点的 NSFET 和纳米线场效应晶体管 (NWFET) 电气特性的影响。我们使用 2-D 自动协方差函数 (ACVF) 生成了 3-D LER 配置文件，该函数考虑了两个自由度，以便在高级 CMOS 技术节点上进行真实的粗糙度分析。对于 NSFET 中 3-D LER 效应的完整研究，我们已经考虑了沿纳米片侧壁以及顶面和底面的粗糙度。我们已经使用 3D TCAD 模拟表明，NSFET 中的侧壁粗糙度对阈值电压和导通电流的失配影响可忽略不计。将 NSFET 的失配性能与用于亚 7nm 技术节点的 NWFET 的失配性能进行比较。NSFET 似乎比这项工作中考虑的 NWFET 更容易受到导通电流不匹配的影响。另一方面，与 NSFET 相比，由于其卓越的栅极全方位控制，NWFET 在存在 LER 的情况下实现了较低的漏极感应势垒降低 (DIBL) 和亚阈值斜率 (SS) 失配。除此之外，还比较了具有不同沟道掺杂模式（例如反转 (IM) 和无结 (JL) 模式）的 FET 与 3-D LER 的匹配性能。