In this work, we investigate the impact of Si-SiO2 interface traps on the performance of negative capacitance transistor, which is a promising emerging technology that aims at achieving a steep sub-threshold slope. Interface traps induced degradation is well known to be one of the major concerns when it comes to reliability. We focus on investigating the impact of different interface trap concentrations on the figures of merit of both the devices and circuits. Our investigation is performed using TCAD models, which are well calibrated against 14nm production quality FinFETs. This allows accurate analysis and modeling of the impact of NC on the electric field across the SiO2 layer. Then, the industry compact model of FinFET (BSIM-CMG) is fully calibrated to reproduce TCAD data. In addition, a physics-based NC model is integrated and solved self-consistently within the BSIM-CMG model in which TCAD data of NC-pFinFETs and NC-nFinFETs are also well matched. This allows studying how interface traps induced degradation can impact circuits. Our results demonstrate that the amplified electric field across the SiO2 layer within NC-pFinFET due to NC effect leads to a higher interface trap concentration. This, in turn, results in a larger degradation in the NC-pFinFET compared to its pFinFET counterpart - when both of these devices are operated at the same nominal supply voltage of the 14nm node. However, at the same interface trap concentration, the NC-pFinFET always exhibits less degradation than the baseline pFinFET due to the former's better electrostatic integrity on account of voltage amplification effect. With respect to circuits, we study both Ring Oscillator (RO) and 6-T SRAM cell circuits. We show how the frequency of RO in the case of NC-FinFET is always less impacted by interface trap induced degradations compared to its counterpart FinFET-based RO. For 6-T SRAM cell, we demonstrate how the key reliability metrics such as hold noise margin, read noise margin, and write noise margin are also less impacted by the induced degradations in NC-FinFET SRAMs compared to the baseline FinFET SRAMs. This is because of the much better electrostatic integrity that NC provides.

中文翻译：

---

接口陷阱对负电容晶体管的影响：器件和电路可靠性


在这项工作中，我们研究了 Si-SiO2 界面陷阱对负电容晶体管性能的影响，这是一项有前景的新兴技术，旨在实现陡峭的亚阈值斜率。众所周知，界面陷阱引起的退化是可靠性方面的主要问题之一。我们重点研究不同界面陷阱浓度对器件和电路品质因数的影响。我们的调查是使用 TCAD 模型进行的，该模型针对 14 纳米生产质量 FinFET 进行了良好校准。这样可以准确分析和建模 NC 对 SiO2 层电场的影响。然后，对 FinFET 的行业紧凑模型 (BSIM-CMG) 进行全面校准，以重现 TCAD 数据。此外，基于物理的 NC 模型在 BSIM-CMG 模型中集成并自洽求解，其中 NC-pFinFET 和 NC-nFinFET 的 TCAD 数据也很好匹配。这允许研究界面陷阱引起的退化如何影响电路。我们的结果表明，由于 NC 效应，NC-pFinFET 内 SiO2 层上的电场被放大，导致界面陷阱浓度更高。反过来，当这两个器件在 14nm 节点的相同标称电源电压下运行时，与 pFinFET 同类器件相比，NC-pFinFET 的性能退化会更大。然而，在相同的界面陷阱浓度下，NC-pFinFET 始终表现出比基准 pFinFET 更少的退化，因为前者由于电压放大效应而具有更好的静电完整性。在电路方面，我们研究了环形振荡器 (RO) 和 6-T SRAM 单元电路。 我们展示了与基于 FinFET 的 RO 相比，NC-FinFET 情况下的 RO 频率如何始终较少受到界面陷阱引起的退化的影响。对于 6-T SRAM 单元，我们演示了与基准 FinFET SRAM 相比，NC-FinFET SRAM 中的关键可靠性指标（例如保持噪声容限、读取噪声容限和写入噪声容限）如何较少受到 NC-FinFET SRAM 诱发退化的影响。这是因为 NC 提供了更好的静电完整性。