In this article, by using neural network, we proposed a method to optimize Fully-Depleted (FD) Silicon-on-Insulator (SOI) Field-Effect-Transistor (FET) structures to maximize the on/off current ratio for 14-nm node (70-nm Gate Pitch) System-on-Chip (SoC) and sequential 3-dimensional integrated circuit (3DIC). Using machine learning method, the neural network accurately predicted the electrical behaviors of 14-nm node FDSOI FETs. Also by using backpropagation and gradient descent method, the device structures were modified to improve on/off current ratios for high performance (HP), low operating power (LOP), and low stand-by power (LSTP) applications. These optimized structures were secured within the process range of conventional FDSOI FETs. Among the optimized parameters, drain-side spacer length ( $L_{spd}$ ), source/drain junction gradient ( $L_{sdj}$ ), and thickness of source/drain epi ( $T_{sd}$ ) showed different behaviors for each application and thickness of buried oxide ( $T_{box}$ ) was maximal in optimization results. The detailed physical analysis was conducted to evaluate these parameters for each application. The neural network based optimization was powerful and efficient while saving time and cost in device design.

中文翻译：

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基于神经网络的 14 纳米节点全耗尽 SOI FET 设计优化，适用于 SoC 和 3DIC 应用

在本文中，我们通过使用神经网络，提出了一种优化全耗尽 (FD) 绝缘体上硅 (SOI) 场效应晶体管 (FET) 结构的方法，以最大化 14 纳米的开/关电流比节点（70 纳米栅极间距）片上系统 (SoC) 和顺序 3 维集成电路 (3DIC)。使用机器学习方法，神经网络准确预测了 14 纳米节点 FDSOI FET 的电气行为。此外，通过使用反向传播和梯度下降方法，对器件结构进行了修改，以提高高性能 (HP)、低运行功率 (LOP) 和低待机功率 (LSTP) 应用的开/关电流比。这些优化的结构在传统 FDSOI FET 的工艺范围内得到保证。在优化的参数中，漏极侧间隔长度（ $L_{spd}$ ), 源/漏结梯度 ( $L_{sdj}$ )，以及源极/漏极外延厚度 ( $T_{sd}$ ) 对每种应用和掩埋氧化物的厚度表现出不同的行为 ( $T_{box}$ ) 的优化结果最大。进行了详细的物理分析以评估每种应用的这些参数。基于神经网络的优化功能强大且高效，同时节省了设备设计的时间和成本。