Wafer level chip scale package (WLCSP) is true chip scale package with low cost by eliminating package substrate. The direct chip-to-board attach through solder joints provides low interconnect inductance and resistance, as well as improved thermal performance. These properties make WLCSP a packaging format well suited for 5G radio frequency (RF) applications where minimized package size and parasitics as well as thermal performance are critical. Due to the dissimilar properties between chip and board, the reliability of WLCSP can be challenging. This article reports a reliability study of WLCSP using 45nm RFSOI technology for 5G RF applications. Dedicated test chips and boards were designed and used for board level reliability tests. The test vehicles passed bHAST and drop test, whereas it is found that temperature cycling on board (TCoB) is challenging for solder joint reliability in some cases. Thorough tests were carried out based on Kelvin test on specially designed individual bump and bump pair structures and developed fail criterion. Finite element modeling was adopted to simulate the reliability performance in different configurations. The impact on reliability performance from bump depopulation, die thickness, bump size, UBM to board pad alignment, and board wiring trace were thoroughly investigated. Based on comprehensive testing and deep understanding of the failure mechanisms, design optimizations for chip, board and interconnect were implemented. WLCSP reliability was significantly improved.

中文翻译：

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了解和提高晶圆级芯片级封装的可靠性：基于 45nm RFSOI 技术的 5G 应用研究

晶圆级芯片级封装 (WLCSP) 是真正的芯片级封装，无需封装基板，成本低。通过焊点直接芯片到板的连接提供了低互连电感和电阻，以及改进的热性能。这些特性使 WLCSP 成为一种非常适合 5G 射频 (RF) 应用的封装格式，在这些应用中，最小化封装尺寸和寄生效应以及热性能至关重要。由于芯片和电路板之间的不同特性，WLCSP 的可靠性可能具有挑战性。本文报告了使用 45nm RFSOI 技术进行 5G RF 应用的 WLCSP 可靠性研究。专门的测试芯片和电路板被设计用于板级可靠性测试。测试车辆通过了 bHAST 和跌落测试，而发现在某些情况下，板载温度循环 (TCoB) 对焊点可靠性具有挑战性。基于开尔文测试对专门设计的单个凸块和凸块对结构进行了彻底的测试，并制定了失败标准。采用有限元建模来模拟不同配置下的可靠性性能。全面研究了凸块数量减少、芯片厚度、凸块尺寸、UBM 与电路板焊盘对齐以及电路板布线轨迹对可靠性性能的影响。在全面测试和深入了解故障机制的基础上，实现了芯片、电路板和互连的设计优化。WLCSP 可靠性得到显着提高。基于开尔文测试对专门设计的单个凸块和凸块对结构进行了彻底的测试，并制定了失败标准。采用有限元建模来模拟不同配置下的可靠性性能。全面研究了凸块数量减少、芯片厚度、凸块尺寸、UBM 与电路板焊盘对齐以及电路板布线轨迹对可靠性性能的影响。在全面测试和深入了解故障机制的基础上，实现了芯片、电路板和互连的设计优化。WLCSP 可靠性得到显着提高。基于开尔文测试对专门设计的单个凸块和凸块对结构进行了彻底的测试，并制定了失败标准。采用有限元建模来模拟不同配置下的可靠性性能。全面研究了凸块数量减少、芯片厚度、凸块尺寸、UBM 与电路板焊盘对齐以及电路板布线轨迹对可靠性性能的影响。在全面测试和深入了解故障机制的基础上，实现了芯片、电路板和互连的设计优化。WLCSP 可靠性得到显着提高。全面研究了凸块数量减少、芯片厚度、凸块尺寸、UBM 与电路板焊盘对齐以及电路板布线轨迹对可靠性性能的影响。在全面测试和深入了解故障机制的基础上，实现了芯片、电路板和互连的设计优化。WLCSP 可靠性得到显着提高。全面研究了凸块数量减少、芯片厚度、凸块尺寸、UBM 与电路板焊盘对齐以及电路板布线轨迹对可靠性性能的影响。在全面测试和深入了解故障机制的基础上，实现了芯片、电路板和互连的设计优化。WLCSP 可靠性得到显着提高。