Achieving frequency- and temperature-independent colossal permittivity (CP) with low dielectric loss is a long-standing challenge for electronic materials, in which the basic issue is understanding the underlying relaxation mechanism. In this paper, taking CaCu₃Ti₄O₁₂ ceramics as an example, CP was ascribed to electron-trapping behaviors at the edge of a double Schottky barrier (DSB). On the one hand, the widely reported origins of CP, i.e. Maxwell–Wagner relaxation and polaronic relaxation, were identified as two aspects of the same bulk conductivity. This caused the insights derived from the commonly employed impedance and admittance spectra to be revisited. On the other hand, hysteresis between CP and external voltages at low temperatures, which was caused by electron filling of interface states, was predicted and experimentally confirmed. This further supported the proposal that CP arose from electron trapping at the DSB. Moreover, multiple relaxations were foreseen when more than one kind of point defect existed in the depletion layers of a DSB. The establishment of intense ‘effective’ relaxation, which was related to shallow traps, was indispensable for achieving CP, while ‘redundant’ relaxation was induced by deep-level defects, resulting in relatively high dielectric loss. Therefore, proper manipulation of the DSB and its related defect structures was crucial for achieving stable CP with sufficiently low dielectric loss.

对于电子材料而言，以低介电损耗实现不依赖于频率和温度的巨大介电常数（CP）是一项长期的挑战，其中基本问题是了解潜在的弛豫机理。本文采用CaCu ₃ Ti ₄ O ₁₂以陶瓷为例，CP归因于双肖特基势垒（DSB）边缘的电子俘获行为。一方面，被广泛报道的CP的起源，即麦克斯韦-瓦格纳弛豫和极化弛豫，被确定为相同体积电导率的两个方面。这导致重新审视了从常用的阻抗和导纳光谱得出的见解。另一方面，预测和实验证实了低温下CP和外部电压之间的磁滞现象，这是由界面态的电子填充引起的。这进一步支持了CP由DSB处的电子俘获引起的提议。此外，当在DSB的耗尽层中存在一种以上的点缺陷时，可以预见到多重弛豫。建立强烈的“有效”放松，它与浅陷阱有关，对于实现CP必不可少，而深层缺陷会引起“冗余”弛豫，从而导致相对较高的介电损耗。因此，对DSB及其相关缺陷结构的正确处理对于获得具有足够低介电损耗的稳定CP至关重要。