In this study, the design of digital logic gates and circuits in ternary logic is presented. The ternary logic is observed to be a better alternative to the traditional binary logic because it offers faster computations, smaller chip area, and lesser interconnects. Thus, it allows designing the low-complex, high-speed, and energy-efficient circuits in future digital design. A novel technique is proposed to design the ternary logic gates using multi-threshold graphene nanoribbon field-effect transistors (GNRFETs). The GNRFET threshold voltage is controlled by the width of the graphene nanoribbon, which is defined by the dimer lines number. Three different inverters are designed namely standard, positive, and negative inverters along with the basic and universal logic gates. Additionally, the ternary half adder and full adder are proposed that further helps to design the complex arithmetic circuits. All the proposed ternary logic circuits have been extensively simulated in SPICE for functional verification and performance analysis. The performance of the proposed ternary logic circuits is compared with the existing designs presented in the literature. The comparison results show that the propagation delay and circuit area of GNRFET-based circuits are reduced with an average of 41.3 and 64%, respectively, than the existing ternary circuits.

中文翻译：

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使用GNRFET的三态逻辑门和电路的设计

在这项研究中，提出了三态逻辑中数字逻辑门和电路的设计。三元逻辑被认为是传统二元逻辑的更好替代方案，因为它提供了更快的计算，更小的芯片面积和更少的互连。因此，它允许在未来的数字设计中设计低复杂度，高速和节能电路。提出了一种使用多阈值石墨烯纳米带场效应晶体管（GNRFET）设计三元逻辑门的新技术。GNRFET阈值电压由石墨烯纳米带的宽度控制，该宽度由二聚体线数定义。设计了三种不同的逆变器，即标准，正和负逆变器以及基本和通用逻辑门。另外，提出了三进制半加法器和全加法器，这进一步有助于设计复杂的算术电路。所有提出的三态逻辑电路均已在SPICE中进行了广泛的仿真，以进行功能验证和性能分析。将所提出的三态逻辑电路的性能与文献中提出的现有设计进行了比较。比较结果表明，与现有的三元电路相比，基于GNRFET的电路的传输延迟和电路面积分别平均减少了41.3％和64％。将所提出的三态逻辑电路的性能与文献中提出的现有设计进行了比较。比较结果表明，与现有的三元电路相比，基于GNRFET的电路的传输延迟和电路面积分别平均减少了41.3％和64％。将所提出的三态逻辑电路的性能与文献中提出的现有设计进行了比较。比较结果表明，与现有的三元电路相比，基于GNRFET的电路的传播延迟和电路面积分别平均减少了41.3％和64％。