In this study, a new tier partitioning algorithm for three-dimensional integrated circuits (3D ICs) using a genetic algorithm (GA) is presented. Design parameters for the proposed 3D IC partitioning method are average layer power density and number of through-silicon vias (TSVs) subject to fixed-outline constraint. The GA with newly introduced crossover and mutation operation, termed as even crossover and complement mutation, is employed for optimisation of design variables. Experimental results exhibit that the authors proposed method reduces the average number of TSVs by 45.75 and 44.68%, as compared to taboo search and simulated annealing-based 3D partitioning methods. It also reduces the average number of TSVs, maximum power density among the layers and average layer area by 28.34, 40.29, and 27.85%, respectively, as compared to thermal-aware 3D partitioning technique. The results of their proposed algorithm demonstrate the efficiency and effectiveness in tier partitioning for 3D ICs over existing methods.

中文翻译：

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基于遗传算法的3D-IC划分方法

在这项研究中，提出了一种使用遗传算法（GA）的三维集成电路（3D IC）的新层划分算法。拟议的3D IC划分方法的设计参数是平均层功率密度和受固定轮廓约束的硅通孔（TSV）的数量。具有新引入的交叉和变异操作的GA（称为偶数交叉和补体变异）用于优化设计变量。实验结果表明，与禁忌搜索和基于模拟退火的3D分区方法相比，作者提出的方法将TSV的平均数量减少了45.75和44.68％。它还将TSV的平均数量，各层之间的最大功率密度和平均层面积分别减少了28.34、40.29和27.85％。与热感知3D分区技术相比。他们提出的算法的结果证明了现有方法对3D IC进行层划分的效率和有效性。