Abstract Gate-stack reliability has been a major roadblock in the realization of InGaAs-channel based logic technology. Excessive charge trapping in the gate-oxide causes time-dependent drift in transistor threshold voltage (Vth). The extent to which Vth drifts under certain stress conditions depends on (i) the defect ground-state energy distributions in the oxide bandgap, and (ii) the specific activation energy distributions for charge capture/emission process. In this work, semi-empirical modelling of ground-state defect energy distributions is revisited to determine the Total Operating Voltage Range of InGaAs-based MOSFETs for a DC-BTI lifetime of 10 years under DC operating conditions. Non-radiative Multiphonon (NMP) theory is subsequently used to describe the microscopic physics of charge (de-)trapping kinetics in terms of activation energy barriers for charge capture (EAc) and emission (EAe) into/from gate-stack defects. These activation energy barriers are visualized using Capture/Emission Time (CET) maps, which are efficient and powerful tools to predict the BTI degradation under different AC operating conditions as well. We demonstrate that the enhanced BTI reliability of a gate-stack with a novel ASM interfacial layer (ASM-IL), as compared to the bilayer gate-stack of Al2O3/HfO2, results from the favorable reconfiguration of the defect energy distribution in the oxide bandgap, as well as their activation energies for capture and emission process.

中文翻译：

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对 InGaAs MOS 栅叠层中的电荷俘获动力学进行广泛评估，以证明改进的 BTI 可靠性

摘要 栅极堆叠可靠性一直是实现基于 InGaAs 通道的逻辑技术的主要障碍。栅极氧化物中过多的电荷俘获会导致晶体管阈值电压 (Vth) 随时间发生漂移。Vth 在某些应力条件下漂移的程度取决于 (i) 氧化物带隙中的缺陷基态能量分布，以及 (ii) 电荷捕获/发射过程的特定活化能分布。在这项工作中，重新审视了基态缺陷能量分布的半经验建模，以确定在直流工作条件下 DC-BTI 寿命为 10 年的 InGaAs 基 MOSFET 的总工作电压范围。非辐射多声子 (NMP) 理论随后用于描述电荷（去）俘获动力学的微观物理学，根据电荷捕获 (EAc) 和发射 (EAe) 进入/从栅堆叠缺陷的激活能垒。这些活化能垒使用捕获/发射时间 (CET) 地图进行可视化，这是预测不同交流操作条件下 BTI 退化的有效且强大的工具。我们证明，与 Al2O3/HfO2 的双层栅叠层相比，具有新型 ASM 界面层 (ASM-IL) 的栅叠层增强的 BTI 可靠性是由于氧化物中缺陷能量分布的有利重新配置带隙，以及它们用于捕获和发射过程的活化能。