An all-OTA analog buffer amplifier configuration capable of driving large resistive loads is presented. The proposed configuration features high input swing, gain tunability, wide-bandwidth, and low design complexity. The concept is validated with simulation results in Cadence Virtuoso using SCL 0.18-μm technology parameters. Using a ±0.9 V power supply, the buffer with a gain of 1, can drive a 1 V_p−p sinusoid into a 50 Ω load with a THD of better than 0.015%, with a 3-dB bandwidth of 1.55 GHz and consumes 9 mW. The proposed configuration is demonstrated with gain values varying from 0.25 V/V to 5 V/V and with different load values 16 Ω to 5.6 kΩ. The voltage gain is tunable over more than a decade with reasonable power levels. With low-gain OTA, the proposed buffer configuration works well without any complex frequency compensation circuit that makes the all-OTA analog buffer amplifier configuration simple compared to the existing buffer amplifiers.

提出了一种能够驱动大阻性负载的全OTA模拟缓冲放大器配置。提议的配置具有高输入摆幅，增益可调性，宽带和低设计复杂度的特点。概念验证使用SCL 0.18仿真结果的Cadence的Virtuoso μ米技术参数。使用±0.9 V电源，增益为1的缓冲器可以驱动1  V _{p - p}正弦波进入50Ω负载，THD优于0.015％，具有1.55 GHz的3dB带宽，功耗为9 mW。所建议的配置通过从0.25 V / V至5 V / V的增益值和不同的16Ω至5.6kΩ负载值进行了演示。在合理的功率水平下，电压增益可以调节十多年。采用低增益OTA时，所建议的缓冲器配置无需任何复杂的频率补偿电路就能很好地工作，与现有的缓冲器放大器相比，它使全OTA模拟缓冲器放大器的配置变得简单。