Dedicated accelerators are being designed to address the huge resource requirement of the deep neural network (DNN) applications. The power, performance and area (PPA) constraints limit the number of MACs available in these accelerators. The convolution layers which require huge number of MACs are often partitioned into multiple iterative sub-tasks. This puts huge pressure on the available system resources such as interconnect and memory bandwidth. The optimal partitioning of the feature maps for these sub-tasks can reduce the bandwidth requirement substantially. Some accelerators avoid off-chip or interconnect transfers by implementing local memories; however, the memory accesses are still performed and a reduced bandwidth can help in saving power in such architectures. In this paper, we propose a first order analytical method to partition the feature maps for optimal bandwidth and evaluate the impact of such partitioning on the bandwidth. This bandwidth can be saved by designing an active memory controller which can perform basic arithmetic operations. It is shown that the optimal partitioning and active memory controller can achieve up to 40% bandwidth reduction.

中文翻译：

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关于部分和对 DNN 加速器中互连带宽和内存访问的影响

专用加速器旨在解决深度神经网络 (DNN) 应用程序的巨大资源需求。功率、性能和面积 (PPA) 限制限制了这些加速器中可用的 MAC 数量。需要大量 MAC 的卷积层通常被划分为多个迭代子任务。这给可用的系统资源（例如互连和内存带宽）带来了巨大压力。这些子任务的特征图的最佳划分可以显着降低带宽需求。一些加速器通过实现本地存储器来避免片外或互连传输；然而，内存访问仍在执行，减少带宽有助于在此类架构中节省功耗。在本文中，我们提出了一种一阶分析方法来划分特征图以获得最佳带宽，并评估这种划分对带宽的影响。通过设计可以执行基本算术运算的有源存储器控制器，可以节省此带宽。结果表明，最佳分区和主动内存控制器可以实现高达 40% 的带宽减少。