In-memory computing (IMC) can eliminate the data movement between processor and memory which is a barrier to the energy-efficiency and performance in Von-Neumann computing. Resistive RAM (RRAM) is one of the promising devices for IMC applications (e.g. integer and Floating Point (FP) operations and random logic implementation) due to low power consumption, fast operation, and small footprint in crossbar architecture. In this paper, we propose FAME, a pipelined FP arithmetic (adder/subtractor) using RRAM crossbar based IMC. A novel shift circuitry is proposed to lower the shift overhead during FP operations. Since 96% of the RRAMs used in our architecture are in High Resistance State (HRS), we propose two approaches namely Shift-At-The-Output (SATO) and Force To VDD (FTV) (ground (FTG)) to mitigate Stuck-at-1 (SA1) failures. In both techniques, the fault-free RRAMs are exploited to perform the computation by using an extra clock cycle. Although performance degrades by 50%, SATO can handle 50% of the faults whereas FTV can handle 99% of the faults in the RRAM-based compute array at low power and area overhead. Simulation results show that the proposed single precision FP adder consumes 335 pJ and 322 pJ for NAND-NAND and NOR-NOR based implementations, respectively. The area overheads of SATO and FTV are 28.5% and 9.5%, respectively.

中文翻译：

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解决内存中浮点计算的弹性

内存计算 (IMC) 可以消除处理器和内存之间的数据移动，这是 Von-Neumann 计算中能源效率和性能的障碍。电阻式 RAM (RRAM) 是 IMC 应用（例如整数和浮点 (FP) 操作和随机逻辑实现）的有前途的器件之一，因为它具有低功耗、快速操作和纵横架构中的小尺寸。在本文中，我们提出了 FAME，一种使用基于 RRAM 交叉开关的 IMC 的流水线 FP 算法（加法器/减法器）。提出了一种新颖的移位电路来降低 FP 操作期间的移位开销。由于我们架构中使用的 96% 的 RRAM 处于高阻状态 (HRS)，我们提出了两种方法，即 Shift-At-The-Output (SATO) 和 Force To VDD (FTV) (ground (FTG)) 以减轻 Stuck -at-1 (SA1) 失败。在这两种技术中，无故障的 RRAM 用于通过使用额外的时钟周期来执行计算。尽管性能下降了 50%，SAT​​O 可以处理 50% 的故障，而 FTV 可以以低功耗和面积开销处理基于 RRAM 的计算阵列中的 99% 故障。仿真结果表明，对于基于 NAND-NAND 和 NOR-NOR 的实现，所提出的单精度 FP 加法器分别消耗 335 pJ 和 322 pJ。SATO和FTV的面积开销分别为28.5%和9.5%。仿真结果表明，对于基于 NAND-NAND 和 NOR-NOR 的实现，所提出的单精度 FP 加法器分别消耗 335 pJ 和 322 pJ。SATO和FTV的面积开销分别为28.5%和9.5%。仿真结果表明，对于基于 NAND-NAND 和 NOR-NOR 的实现，所提出的单精度 FP 加法器分别消耗 335 pJ 和 322 pJ。SATO和FTV的面积开销分别为28.5%和9.5%。