In this work, we present the design and simulation of a novel structure of In_0.53Ga_0.43As/InP based hetero junction tunnel field effect transistor (HTFET). The proposed HTFET employs two gates: the conventional main gate and a pseudo split gate (PSG) at the drain side. The PSG is placed at the top of the drain region with the same equivalent oxide thickness (EOT) and work function as that of the main gate at an optimized separation from gate electrode. The PSG is not an active gate and it is not connected to either V_DD or gate voltage. Two dimensional simulation study has revealed that the proposed device suppresses ambipolar current by ~10 orders of magnitude as compared to a HTFET without overlap and by >7 orders as compared to overlapping gate on drain HTFET (OGD‐HTFET). The PSG‐based HTFET (PSG‐HTFET) also exhibits lesser total gate capacitance as compared to OGD TFET. The proposed PSG‐HTFET offers much better ambipolar suppression even at higher drain doping and lower EOT, as compared to OGD‐HTFET. Further, the PSG‐HTFET exhibits 50% and 40% lesser fall and rise propagation delays respectively as compared to the OGD‐HTEFT. Further, the voltage overshoot and undershoot have also been suppressed in the proposed PSG‐HTFET. The scalability analysis shows that the PSG‐HTFET has better scalability in terms of ambipolar suppression, total gate capacitance, and propagation delays.

中文翻译：

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伪分栅In0.53Ga0.47As / InP异质结隧道FET：设计与分析

在这项工作中，我们介绍了基于In _0.53 Ga _0.43 As / InP的异质结隧道场效应晶体管（HTFET）的新型结构的设计和仿真。所提出的HTFET在漏极侧采用两个栅极：常规的主栅极和伪分裂栅极（PSG）。PSG以相同的等效氧化物厚度（EOT）放置在漏极区的顶部，并以与栅极最佳的间距与主栅极具有相同的等效功。PSG不是有源门，也未连接到任何一个V _DD或栅极电压。二维仿真研究表明，与无重叠的HTFET相比，拟议的器件将双极性电流抑制了约10个数量级，与漏极HTFET（OGD-HTFET）的重叠栅极相比，抑制了双极性电流的> 7个数量级。与OGD TFET相比，基于PSG的HTFET（PSG-HTFET）还具有较小的总栅极电容。与OGD-HTFET相比，即使在更高的漏极掺杂和更低的EOT情况下，拟议的PSG-HTFET也能提供更好的双极性抑制。此外，与OGD-HTEFT相比，PSG-HTFET的下降和上升传播延迟分别减少了50％和40％。此外，建议的PSG-HTFET中的电压过冲和下冲也得到了抑制。可扩展性分析表明，PSG‐HTFET在双极性抑制，总栅极电容，