The voltage level converters (LCs) are required to attain optimized power consumption by interfacing two or more supply voltage domains in Systems-on-Chip (SoC) applications. The voltage level-up conversion can be easily and effectively achieved by the use of buffer structures. Hence this article proposes two buffer-based LCs, namely transmission gate buffer level converter (TGBLC) and stacked PMOS buffer level converter (SPBLC), based on voltage stepping technique. The energy-efficient transmission gate (TG) and stacked PMOS (SP) structures are proposed to define voltage steps in the buffer and ensure a wider voltage conversion range with high speed. The LCs are implemented in 0.18 \(\mu \)m technology and their performance metrics are verified using a Spectre circuit simulator. The simulation results show that TGBLC and SPBLC can convert a low input voltage of 600 and 550 mV to 1.8 V, respectively. For the target input voltage of 0.8 V with frequency of 1 MHz, the TGBLC and SPBLC exhibit an improved delay of 7.3 and 7.1 ns with an energy consumption of 9.66 and 6.66 pJ per transition, respectively. It is noted from the experimental results that the proposed LCs are suitable for applications where simplicity and energy efficiency/low power with a wider conversion range is preferred.

通过在片上系统（SoC）应用中连接两个或多个电源电压域，需要电压电平转换器（LC）来实现优化的功耗。通过使用缓冲器结构可以容易且有效地实现电压升压转换。因此，本文基于电压步进技术，提出了两个基于缓冲器的LC，即传输门缓冲器电平转换器（TGBLC）和堆叠式PMOS缓冲器电平转换器（SPBLC）。提出了高能效的传输门（TG）和堆叠的PMOS（SP）结构，以定义缓冲器中的电压阶跃，并确保较宽的高速电压转换范围。LC以0.18 \（\ mu \）实现使用Spectre电路模拟器验证了该技术及其性能指标。仿真结果表明，TGBLC和SPBLC可以分别将600和550 mV的低输入电压转换为1.8V。对于频率为1 MHz的0.8 V的目标输入电压，TGBLC和SPBLC的延迟改善为7.3 ns和7.1 ns，每次转换分别消耗9.66和6.66 pJ的能量。从实验结果中可以看出，所提出的LC适用于优先考虑简单性和能效/低功率且转换范围较大的应用。