Excessive scaling of complementary metal oxide semiconductor (CMOS) technology is the main reason of large power dissipation in electronic circuits. Very large-scale integration (VLSI) industry has chosen an alternative option known as fin-shaped field effect transistor (FinFET) technology to mitigate the large power dissipation. FinFET is a multi-gate transistor which dissipates less leakage power as compared to CMOS transistors, but it does not completely resolve the problem of power dissipation. So, leakage reduction approaches are always required to mitigate the impact of power dissipation. In this paper, cascaded leakage control transistors (CLCT) leakage reduction technique is proposed using FinFET transistors. CLCT approach is tested for basic static logic circuits like inverter, 2-input NAND and NOR gates and compared with the existing leakage reduction techniques for leakage power dissipation and delay calculations at 16 and 14 nm technology nodes using Cadence tools. CLCT approach shows the effective reduction of leakage power with minimum delay penalty. As the domino logic gates are widely used in large memories and high-speed processors therefore, CLCT approach is further utilized for footless domino logic (FLDL) and compared with the available methods at 14nm technology node. CLCT approach reduces 35.16% power dissipation as compared to the conventional domino OR logic. Temperature and multiple parallel fin variations are estimated for the domino OR logic to check its reliable operation. CLCT approach has high-noise tolerance capability in term of unity noise gain (UNG) for domino OR logic as compared to the other methods.

中文翻译：

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FinFET Domino OR Logic 的新型低功耗技术

互补金属氧化物半导体（CMOS）技术的过度缩放是电子电路中功耗大的主要原因。超大规模集成 (VLSI) 行业选择了一种称为鳍形场效应晶体管 (FinFET) 技术的替代选项，以减轻大功率耗散。FinFET 是一种多栅极晶体管，与 CMOS 晶体管相比，其泄漏功率较小，但并不能完全解决功耗问题。因此，始终需要减少泄漏的方法来减轻功耗的影响。在本文中，使用 FinFET 晶体管提出了级联泄漏控制晶体管 (CLCT) 泄漏减少技术。CLCT 方法已针对基本静态逻辑电路进行测试，例如逆变器、2 输入 NAND 和 NOR 门，并与使用 Cadence 工具在 16 和 14 nm 技术节点进行泄漏功耗和延迟计算的现有泄漏减少技术进行比较。CLCT 方法显示了以最小延迟损失有效降低泄漏功率。由于多米诺逻辑门广泛用于大型存储器和高速处理器，因此，CLCT 方法进一步用于无脚多米诺逻辑（FLDL），并与 14 的可用方法进行比较纳米技术节点。与传统的多米诺或逻辑相比，CLCT 方法降低了 35.16% 的功耗。为多米诺逻辑或逻辑估计温度和多个平行翅片变化，以检查其可靠运行。与其他方法相比，CLCT 方法在多米诺或逻辑的单位噪声增益 (UNG) 方面具有高噪声容限能力。