Technological advances allow the production of increasingly complex electronic systems. Nevertheless, technology and voltage scaling increased dramatically the susceptibility of new devices not only to Single Bit Upsets (SBU), but also to Multiple Bit Upsets (MBU). In safety critical applications, it is mandatory to provide fault-tolerant systems, providing high reliability while meeting applications requirements. The problem of reliability is particularly expressed within the memory which represents more than 80 % of systems on chips. To tackle this problem we propose a new memory reliability techniques referred to as DPSR: Double Parity Single Redundancy. DPSR is designed to enhance computing systems resilience to SBU and MBU. Based on a thorough fault injection experiments, DPSR shows promising results; It detects and corrects more than 99.6 % of encountered MBU and has an average time overhead of less than 3 %.

技术的进步使生产越来越复杂的电子系统成为可能。尽管如此，技术和电压缩放显着提高了新器件不仅对单位比特高位（SBU），而且对于多位最高位（MBU）的敏感性。在安全关键型应用中，必须提供容错系统，在满足应用要求的同时提供高可靠性。可靠性问题尤其体现在内存中，内存占芯片上系统的80％以上。为了解决这个问题，我们提出了一种新的存储器可靠性技术，称为DPSR：双奇偶校验单冗余。DPSR旨在增强计算系统对SBU和MBU的弹性。基于彻底的故障注入实验，DPSR显示出令人鼓舞的结果；它可以检测并纠正99多个。