We investigated the circuit performance of gate-all-around (GAA) CMOS inverters including strain for various sub-7 nm technology node device architectures. Multi-stacked GAA structure can compensate for the small cross-sectional area to increase the current drive per device footprint. However, due to the increase in parasitic capacitance, delay gain may be marginal. Nanosheets provide a large effective width per footprint and exhibits tolerance to parasitic components compared to nanowires. We show the logic performance of strained GAA CMOS for various number of stacked channel levels, strain conditions, and load capacitance conditions. Device simulations include quantum effects in the confined channel and strain-dependent multi-valley mobility models. Carrier mobility curves and current enhancement by strain are validated by comparison with experimental and advanced simulation results in the literature, respectively. Device combinations that effectively reduce the inverter dela...

中文翻译：

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应变对多堆叠全栅CMOS反相器性能的影响

我们研究了全栅极（GAA）CMOS反相器的电路性能，包括适用于各种7纳米以下技术节点设备架构的应变。多堆叠GAA结构可以补偿较小的横截面积，从而增加每个设备占位面积的电流驱动器。但是，由于寄生电容的增加，延迟增益可能很小。与纳米线相比，纳米片在每个足迹上提供了较大的有效宽度，并表现出对寄生元件的耐受性。我们展示了在各种数量的堆叠通道级，应变条件和负载电容条件下，应变GAA CMOS的逻辑性能。器件模拟包括受限通道中的量子效应和依赖应变的多谷迁移率模型。通过与文献中的实验和高级仿真结果进行比较，分别验证了载流子迁移率曲线和应变引起的电流增强。有效减少逆变器延迟的设备组合