This communication describes a gate leakage compensation technique to ensure wide-temperature operation and wide-supply regulation of traditional self-cascode based voltage references in deep nanometre nodes ( < 65 nm ). Extensive simulations in 28 nm ultra-thin buried oxide fully depleted silicon-on-insulator CMOS process show that the proposed 4-transistor topology can operate down to 0.2 V, generating a reference voltage of 98.2 mV with mean and best temperature coefficients of 68.9 and 18.2 ppm / ° C , respectively, from − 40 to 120 ° C .

中文翻译：

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基于自共源共栅的电压基准的栅极泄漏补偿技术

该通讯描述了一种栅极泄漏补偿技术，以确保深纳米节点 (< 65 nm) 中传统基于自共源共栅的电压基准的宽温度操作和宽电源调节。在 28 nm 超薄掩埋氧化物完全耗尽绝缘体上硅 CMOS 工艺中的广泛模拟表明，所提出的 4 晶体管拓扑可以在低至 0.2 V 的电压下工作，产生 98.2 mV 的参考电压，平均和最佳温度系数为 68.9 和18.2 ppm/°C，分别为 - 40 至 120°C。