The current mobile applications have rapidly growing memory footprints, posing a great challenge for memory system design. Insufficient DRAM main memory will incur frequent data swaps between memory and storage, a process that hurts performance, consumes energy, and deteriorates the write endurance of typical flash storage devices. Alternately, a larger DRAM has higher leakage power and drains the battery faster. Furthermore, DRAM scaling trends make further growth of DRAM in the mobile space prohibitive due to cost. Emerging nonvolatile memory (NVM) has the potential to alleviate these issues due to its higher capacity per cost than DRAM and minimal static power. Recently, a wide spectrum of NVM technologies, including phase-change memories (PCMs), memristor, and 3-D XPoint has emerged. Despite the mentioned advantages, NVM has longer access latency compared to DRAM and NVM writes can incur higher latencies and wear costs. Therefore, the integration of these new memory technologies in the memory hierarchy requires a fundamental rearchitecting of traditional system designs. In this work, we propose a hardware-accelerated memory manager (HMMU) that addresses in a flat address space, with a small partition of the DRAM reserved for subpage block-level management. We design a set of data placement and data migration policies within this memory manager such that we may exploit the advantages of each memory technology. By augmenting the system with this HMMU, we reduce the overall memory latency while also reducing writes to the NVM. The experimental results show that our design achieves a 39% reduction in energy consumption with only a 12% performance degradation versus an all-DRAM baseline that is likely untenable in the future.

中文翻译：

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未来移动混合内存系统的硬件内存管理

当前的移动应用程序内存占用快速增长，对内存系统设计提出了巨大挑战。DRAM主存不足会导致内存和存储之间频繁的数据交换，这一过程会损害性能、消耗能源并降低典型闪存设备的写入耐久性。或者，更大的 DRAM 具有更高的泄漏功率并且更快地耗尽电池。此外，由于成本原因，DRAM 的扩展趋势使得 DRAM 在移动领域的进一步增长令人望而却步。新兴的非易失性存储器 (NVM) 有可能缓解这些问题，因为它的单位成本容量比 DRAM 更高，并且静态功耗最低。最近，出现了广泛的 NVM 技术，包括相变存储器 (PCM)、忆阻器和 3-D XPoint。尽管有上述优点，与 DRAM 相比，NVM 具有更长的访问延迟，并且 NVM 写入会导致更高的延迟和磨损成本。因此，在存储器层次结构中集成这些新的存储器技术需要对传统系统设计进行根本性的重构。在这项工作中，我们提出了一种硬件加速内存管理器 (HMMU)，它在平面地址空间中寻址，并为子页块级管理保留了一小部分 DRAM。我们在此内存管理器中设计了一组数据放置和数据迁移策略，以便我们可以利用每种内存技术的优势。通过使用此 HMMU 增强系统，我们减少了整体内存延迟，同时减少了对 NVM 的写入。