Multicore architectures are widely adopted in the emerging real-time applications, such as autonomous vehicles and robotics, where latency is required to be both bounded in the worst case (i.e., time predictability) and low. With the number of processors growing, the conventional memory interconnects, i.e., shared bus, crossbar, and network-on-chip (NoC), suffer high latency due to the increasing logic size of their centralized arbiter, which is deployed for time predictability. In this article, we introduce a novel distributed multimemory interconnect, Meshed Bluetree, and explain its operation. Constructed by coupling a router network with multiple Bluetree-based memory architectures in parallel, Meshed Bluetree allows simultaneous access to multiple memory modules. We present the analysis for the predictable timing behavior of memory access to bound the worst case. The evaluation of FPGA with synthetic memory workloads and real-world benchmarks demonstrates the effectiveness of our work, i.e., as the number of memory modules increases, the latency is reduced with the same scale. This work reports the first time-predictable distributed multimemory interconnect, significantly contributing to multicore real-time systems.

中文翻译：

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Meshed Bluetree：多核架构的时间可预测多内存互连

多核架构在新兴的实时应用程序中被广泛采用，例如自动驾驶汽车和机器人技术，在这些应用程序中，延迟需要在最坏情况下（即时间可预测性）和低限制。随着处理器数量的增加，传统的存储器互连，即共享总线、交叉开关和片上网络 (NoC)，由于其集中仲裁器的逻辑大小不断增加而遭受高延迟，这是为了时间可预测性而部署的。在本文中，我们介绍了一种新颖的分布式多内存互连 Meshed Bluetree，并解释了其操作。通过将路由器网络与多个基于 Bluetree 的内存架构并行耦合而构建，Meshed Bluetree 允许同时访问多个内存模块。我们对内存访问的可预测时序行为进行了分析，以限制最坏情况。使用合成内存工作负载和实际基准对 FPGA 进行的评估证明了我们工作的有效性，即随着内存模块数量的增加，延迟以相同的规模减少。这项工作报告了第一个时间可预测的分布式多内存互连，对多核实时系统做出了重大贡献。